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| author | Clifford Wolf <clifford@clifford.at> | 2018-01-19 16:20:40 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-01-19 16:20:40 +0100 |
| commit | 9337e4999dcd32530c15cb618cd106698680e431 (patch) | |
| tree | 2c4ff2fa50c2ff05bdda37afb4811d0b10f9e43b /passes | |
| parent | 54aeca0983484644249dafa98416df15ec4ab74b (diff) | |
| download | yosys-9337e4999dcd32530c15cb618cd106698680e431.tar.gz yosys-9337e4999dcd32530c15cb618cd106698680e431.tar.bz2 yosys-9337e4999dcd32530c15cb618cd106698680e431.zip | |
Improve log messages in equiv_make
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/equiv/equiv_make.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index 40ca42621..b20463777 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -260,11 +260,11 @@ struct EquivMakeWorker for (int i = 0; i < wire->width; i++) { if (undriven_bits.count(assign_map(SigBit(gold_wire, i)))) { - log(" Skipping signal bit %d: undriven on gold side.\n", i); + log(" Skipping signal bit %s [%d]: undriven on gold side.\n", id2cstr(gold_wire->name), i); continue; } if (undriven_bits.count(assign_map(SigBit(gate_wire, i)))) { - log(" Skipping signal bit %d: undriven on gate side.\n", i); + log(" Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i); continue; } equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); |