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* Added %D and %c select commandsClifford Wolf2014-06-141-2/+20
* fixed cell array handling of positional argumentsClifford Wolf2014-06-071-2/+11
* Add support for cell arraysClifford Wolf2014-06-071-0/+34
* added tee cmdClifford Wolf2014-06-032-0/+89
* Fixed log messages in memory_dffClifford Wolf2014-06-011-0/+2
* added log_header to miter and expose pass, show cell type for exposed portsJohann Glaser2014-05-282-3/+9
* be more verbose when techmap yielded processesJohann Glaser2014-05-261-1/+5
* Fixed bug in opt_reduce (see vloghammer issue_044)Clifford Wolf2014-05-121-1/+4
* fixed syntax error in dot file created by "show" commandClifford Wolf2014-05-101-1/+1
* Fixed performance problem in opt_mux with nets driven by many conflicting dri...Clifford Wolf2014-03-191-1/+6
* Small improvement in SAT log messagesClifford Wolf2014-03-131-3/+3
* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-131-0/+1
* - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar...Siesh1oo2014-03-123-3/+5
* OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/...Clifford Wolf2014-03-111-2/+3
* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-114-3/+11
* Fixed memory corruption in passes/abc/blifparse.ccClifford Wolf2014-03-111-1/+1
* Fixed dumping of timing() { .. } block in libparseClifford Wolf2014-03-091-2/+3
* Verbose reading of liberty and constr files in ABC passClifford Wolf2014-03-091-2/+2
* Fixed bug in freduce commandClifford Wolf2014-03-071-0/+30
* Some minor code cleanups in freduce commandClifford Wolf2014-03-071-5/+5
* Added freduce -dumpClifford Wolf2014-03-061-1/+24
* Added freduce -stopClifford Wolf2014-03-061-3/+18
* Fixed undef handling in opt_reduceClifford Wolf2014-03-061-2/+2
* Added techmap -max_iter optionClifford Wolf2014-03-061-0/+10
* fixed freduce for Minisat::SimpSolver: use frozen_literal()Clifford Wolf2014-03-031-2/+2
* Fixed const folding of $bu0 cellsClifford Wolf2014-02-271-0/+1
* Fixed bug (typo) in passes/opt/opt_const.ccClifford Wolf2014-02-221-1/+1
* Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arstClifford Wolf2014-02-211-2/+6
* Added _TECHMAP_REPLACE_ feature to techmapClifford Wolf2014-02-201-4/+21
* Added "extract -ignore_parameters" and "extract -ignore_param ..."Clifford Wolf2014-02-201-0/+79
* Added "extract -map %<design_name>"Clifford Wolf2014-02-201-10/+30
* Added "design -push" and "design -pop"Clifford Wolf2014-02-201-8/+45
* Added connwrappers commandClifford Wolf2014-02-202-0/+206
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-181-49/+93
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| * Added "sat -dump_cnf"Clifford Wolf2014-02-181-5/+34
| * Coding style corrections in SatHelper::dump_model_to_vcd()Clifford Wolf2014-02-181-31/+31
| * Added "sat -initsteps"Clifford Wolf2014-02-181-14/+29
* | Added techmap support for _TECHMAP_CONNMAP_*_Clifford Wolf2014-02-181-0/+39
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* Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanupsClifford Wolf2014-02-171-5/+9
* Added "-dump_fail_to_vcd" argument to SAT solverAndrew Zonenberg2014-02-171-0/+114
* Better preserve wires when flattening (in comparison to techmap)Clifford Wolf2014-02-171-12/+12
* Added some additional checks to techmapClifford Wolf2014-02-161-0/+14
* Added CONSTMSK and CONSTVAL feature to techmapClifford Wolf2014-02-161-0/+23
* Fixed handling of "keep" attribute on wires in opt_cleanClifford Wolf2014-02-161-2/+2
* Fixed use of selection in splitnets commandClifford Wolf2014-02-161-1/+1
* Added recursion support to techmapClifford Wolf2014-02-161-260/+262
* Added != support for relational select patternClifford Wolf2014-02-161-1/+7
* Added iopadmap -bitsClifford Wolf2014-02-151-14/+48
* Fixed dfflibmap for cell libraries with no set-reset-ffClifford Wolf2014-02-151-1/+1
* Fixed opt_const handling of double invert with non-1 output widthClifford Wolf2014-02-151-1/+1