index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
passes
Commit message (
Expand
)
Author
Age
Files
Lines
*
opt_mem_priority: Fix non-ascii char in help message.
Marcelina Kościelnicka
2021-12-09
1
-1
/
+1
*
sta: very crude static timing analysis pass
Lofty
2021-11-25
3
-30
/
+341
*
show: Fix wire bit indexing.
Marcelina Kościelnicka
2021-11-12
1
-3
/
+16
*
Merge pull request #3077 from YosysHQ/claire/genlib
Claire Xen
2021-11-10
1
-21
/
+40
|
\
|
*
Spelling fix in abc.cc
Claire Xen
2021-11-10
1
-1
/
+1
|
*
Add genlib support to ABC command
Claire Xenia Wolf
2021-11-10
1
-21
/
+40
*
|
iopadmap: Fix ebmarassing typo
Marcelina Kościelnicka
2021-11-10
1
-1
/
+1
*
|
iopadmap: Add native support for negative-polarity output enable.
Marcelina Kościelnicka
2021-11-09
1
-7
/
+22
*
|
gowin: widelut support (#3042)
Pepijn de Vos
2021-11-06
1
-2
/
+8
|
/
*
Make it work on all
Miodrag Milanovic
2021-11-05
1
-2
/
+4
*
Correct way of setting maybe_unsused on labels
Miodrag Milanovic
2021-11-05
1
-4
/
+2
*
flatten: Keep sigmap around between flatten_cell invocations.
Marcelina Kościelnicka
2021-11-02
1
-3
/
+4
*
proc_dff: Emit $aldff.
Marcelina Kościelnicka
2021-10-27
1
-32
/
+7
*
dfflegalize: Refactor, add aldff support.
Marcelina Kościelnicka
2021-10-27
1
-973
/
+889
*
verilog: use derived module info to elaborate cell connections
Zachary Snow
2021-10-25
2
-1
/
+7
*
Split out logic for reprocessing an AstModule
Rupert Swarbrick
2021-10-25
1
-1
/
+1
*
Change implicit conversions from bool to Sig* to explicit.
Marcelina Kościelnicka
2021-10-21
1
-4
/
+6
*
extract_reduce: Refactor and fix input signal construction.
Marcelina Kościelnicka
2021-10-21
1
-63
/
+34
*
dfflegalize: remove redundant check for initialized dlatch
Paul Annesley
2021-10-17
1
-4
/
+0
*
FfData: some refactoring.
Marcelina Kościelnicka
2021-10-07
7
-87
/
+48
*
Hook up $aldff support in various passes.
Marcelina Kościelnicka
2021-10-02
3
-4
/
+16
*
zinit: Refactor to use FfData.
Marcelina Kościelnicka
2021-10-02
1
-101
/
+38
*
kernel/ff: Refactor FfData to enable FFs with async load.
Marcelina Kościelnicka
2021-10-02
5
-130
/
+220
*
simplemap: refactor to use FfData.
Marcelina Kościelnicka
2021-10-02
2
-287
/
+20
*
abc9: make re-entrant (#2993)
Eddie Hung
2021-09-09
2
-9
/
+9
*
abc9: holes module to instantiate cells with NEW_ID (#2992)
Eddie Hung
2021-09-09
1
-1
/
+1
*
abc9: replace cell type/parameters if derived type already processed (#2991)
Eddie Hung
2021-09-09
1
-6
/
+22
*
opt_merge: Remove and reinsert init when connecting nets.
Marcelina Kościelnicka
2021-08-22
1
-3
/
+4
*
opt_clean: Make the init attribute follow the FF's Q.
Marcelina Kościelnicka
2021-08-22
1
-0
/
+24
*
proc_prune: Make assign removal and promotion per-bit, remember promoted bits.
Marcelina Kościelnicka
2021-08-14
1
-40
/
+25
*
Add opt_mem_widen pass.
Marcelina Kościelnicka
2021-08-14
3
-0
/
+110
*
memory_share: Add -nosat and -nowiden options.
Marcelina Kościelnicka
2021-08-14
2
-10
/
+41
*
memory_dff: Recognize soft transparency logic.
Marcelina Kościelnicka
2021-08-13
1
-7
/
+451
*
Add new opt_mem_priority pass.
Marcelina Kościelnicka
2021-08-13
3
-2
/
+114
*
Merge pull request #2932 from YosysHQ/mwk/logger-check-expected
Miodrag Milanović
2021-08-13
1
-0
/
+9
|
\
|
*
logger: Add -check-expected subcommand.
Marcelina Kościelnicka
2021-08-12
1
-0
/
+9
*
|
memory_share: Pass addresses through sigmap_xmux everywhere.
Marcelina Kościelnicka
2021-08-13
1
-20
/
+25
|
/
*
memory_dff: Recognize read ports with reset / initial value.
Marcelina Kościelnicka
2021-08-11
1
-7
/
+0
*
proc_memwr: Use the v2 memwr cell.
Marcelina Kościelnicka
2021-08-11
1
-9
/
+19
*
Add v2 memory cells.
Marcelina Kościelnicka
2021-08-11
7
-10
/
+14
*
kernel/mem: Introduce transparency masks.
Marcelina Kościelnicka
2021-08-11
4
-70
/
+45
*
Refactor common parts of SAT-using optimizations into a helper.
Marcelina Kościelnicka
2021-08-09
3
-150
/
+40
*
opt_merge: Use FfInitVals.
Marcelina Kościelnicka
2021-08-08
1
-27
/
+8
*
memory_share: Don't skip ports with EN wired to input for SAT sharing.
Marcelina Kościelnicka
2021-08-04
1
-3
/
+1
*
memory_bram: Move init data swizzling before other swizzling.
Marcelina Kościelnicka
2021-08-03
1
-18
/
+18
*
memory_bram: Some refactoring
Marcelina Kościelnicka
2021-08-01
1
-196
/
+174
*
proc_rmdead: use explicit pattern set when there are no wildcards
Zachary Snow
2021-07-29
1
-2
/
+63
*
opt_lut: Allow more than one -dlogic per cell type.
Marcelina Kościelnicka
2021-07-29
1
-23
/
+30
*
memory: Introduce $meminit_v2 cell, with EN input.
Marcelina Kościelnicka
2021-07-28
3
-2
/
+3
*
proc: Run opt_expr at the end
Marcelina Kościelnicka
2021-07-27
1
-0
/
+11
[next]