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| author | Eddie Hung <eddie@fpgeh.com> | 2021-09-09 10:05:55 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-09-09 10:05:55 -0700 |
| commit | f03e2c30aa3ad92bffb7ecd7179fe859d1b993b0 (patch) | |
| tree | 46a0d4a5467a936ae88d56dd310d5c64326798ab /passes | |
| parent | 50be8fd0c23856be7afa28527fe4f30dcc975c87 (diff) | |
| download | yosys-f03e2c30aa3ad92bffb7ecd7179fe859d1b993b0.tar.gz yosys-f03e2c30aa3ad92bffb7ecd7179fe859d1b993b0.tar.bz2 yosys-f03e2c30aa3ad92bffb7ecd7179fe859d1b993b0.zip | |
abc9: replace cell type/parameters if derived type already processed (#2991)
* Add close bracket
* Add testcase
* Replace cell type/param if in unmap_design
* Improve abc9_box error message too
* Update comment as per review
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 28 |
1 files changed, 22 insertions, 6 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 4b5def5eb..c3eaa70d1 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -180,8 +180,16 @@ void prep_hier(RTLIL::Design *design, bool dff_mode) continue; } else { - if (!derived_module->get_bool_attribute(ID::abc9_box) && !derived_module->get_bool_attribute(ID::abc9_bypass)) + if (!derived_module->get_bool_attribute(ID::abc9_box) && !derived_module->get_bool_attribute(ID::abc9_bypass)) { + if (unmap_design->module(derived_type)) { + // If derived_type is present in unmap_design, it means that it was processed previously, but found to be incompatible -- e.g. if + // it contained a non-zero initial state. In this case, continue to replace the cell type/parameters so that it has the same properties + // as a compatible type, yet will be safely unmapped later + cell->type = derived_type; + cell->parameters.clear(); + } continue; + } } if (!unmap_design->module(derived_type)) { @@ -442,7 +450,14 @@ void prep_dff(RTLIL::Design *design) if (!inst_module->get_bool_attribute(ID::abc9_flop)) continue; log_assert(!inst_module->get_blackbox_attribute(true /* ignore_wb */)); - log_assert(cell->parameters.empty()); + if (!cell->parameters.empty()) + { + // At this stage of the ABC9 flow, cells instantiating (* abc9_flop *) modules must not contain any parameters -- instead it should + // be instantiating the derived module which will have had any parameters constant-propagated. + // This task is expected to be performed by `abc9_ops -prep_hier`, but it looks like it failed to do so for this design. + // Please file a bug report! + log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_flop *)\n", log_id(cell->name), log_id(cell->type)); + } modules_sel.select(inst_module); } } @@ -783,10 +798,11 @@ void prep_xaiger(RTLIL::Module *module, bool dff) continue; if (!cell->parameters.empty()) { - // At this stage of the ABC9 flow, all modules must be nonparametric, because ABC itself requires concrete netlists, and the presence of - // parameters implies a non-concrete netlist. This means an (* abc9_box *) parametric module but due to a bug somewhere this hasn't been - // uniquified into a concrete parameter-free module. This is a bug, and a bug report would be welcomed. - log_error("Not expecting parameters on module '%s' marked (* abc9_box *)\n", log_id(cell_name)); + // At this stage of the ABC9 flow, cells instantiating (* abc9_box *) modules must not contain any parameters -- instead it should + // be instantiating the derived module which will have had any parameters constant-propagated. + // This task is expected to be performed by `abc9_ops -prep_hier`, but it looks like it failed to do so for this design. + // Please file a bug report! + log_error("Not expecting parameters on cell '%s' instantiating module '%s' marked (* abc9_box *)\n", log_id(cell_name), log_id(cell->type)); } log_assert(box_module->get_blackbox_attribute()); |