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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-08-04 03:33:41 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-08-04 04:47:43 +0200 |
| commit | 63f9e0544fcb793dcc47b9c5a6d8b0e46d84a225 (patch) | |
| tree | 5df7f48932acffb8a2e1fc335878fa9d94ae30ea /passes | |
| parent | d8b0c3277fb778a1d613dde1fd2d1c47e947d01b (diff) | |
| download | yosys-63f9e0544fcb793dcc47b9c5a6d8b0e46d84a225.tar.gz yosys-63f9e0544fcb793dcc47b9c5a6d8b0e46d84a225.tar.bz2 yosys-63f9e0544fcb793dcc47b9c5a6d8b0e46d84a225.zip | |
memory_share: Don't skip ports with EN wired to input for SAT sharing.
Fixes #2912.
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/memory/memory_share.cc | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 846583c2c..4e6a30ef1 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -288,8 +288,7 @@ struct MemoryShareWorker for (auto bit : bits) if (bit == RTLIL::State::S1) goto port_is_always_active; - if (modwalker.has_drivers(bits)) - eligible_ports.insert(i); + eligible_ports.insert(i); port_is_always_active:; } @@ -310,7 +309,6 @@ struct MemoryShareWorker if (checked_ports.count(i)) continue; - std::vector<int> group; group.push_back(i); |