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| author | Rupert Swarbrick <rswarbrick@gmail.com> | 2021-10-19 18:43:30 -0600 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-10-25 18:25:50 -0700 |
| commit | bd16d01c0eed5c96a241e6ee9e56b8f7890319a1 (patch) | |
| tree | b55271d7943d0a2482a3a3cbc708ed30bc8d5af2 /passes | |
| parent | ee230f2bb9a2fe473b0ddb6bcfa30a15b0f07c88 (diff) | |
| download | yosys-bd16d01c0eed5c96a241e6ee9e56b8f7890319a1.tar.gz yosys-bd16d01c0eed5c96a241e6ee9e56b8f7890319a1.tar.bz2 yosys-bd16d01c0eed5c96a241e6ee9e56b8f7890319a1.zip | |
Split out logic for reprocessing an AstModule
This will enable other features to use same core logic for replacing an
existing AstModule with a newly elaborated version.
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/hierarchy/hierarchy.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 650036580..1e69ab903 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -554,7 +554,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check // If any interface instances or interface ports were found in the module, we need to rederive it completely: if ((if_expander.interfaces_in_module.size() > 0 || has_interface_ports) && !module->get_bool_attribute(ID::interfaces_replaced_in_module)) { - module->reprocess_module(design, if_expander.interfaces_in_module); + module->expand_interfaces(design, if_expander.interfaces_in_module); return did_something; } |