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* Add techmap_autopurge attribute, fixes #1381Clifford Wolf2019-09-191-5/+49
* Added extractinv passMarcin Kościelnicki2019-09-192-0/+124
* Explicitly order function argumentsEddie Hung2019-09-131-4/+15
* Add -match-init option to dff2dffs.Marcin Kościelnicki2019-09-111-3/+26
* techmap: Add support for extracting init values of portsMarcin Kościelnicki2019-09-071-1/+70
* Merge pull request #1312 from YosysHQ/xaig_arrivalEddie Hung2019-09-051-42/+16
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| * Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-301-16/+10
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| * \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-301-1/+1
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| * | | Use a dummy box file if none specifiedEddie Hung2019-08-281-3/+8
| * | | Merge branch 'eddie/xilinx_srl' into xaig_arrivalEddie Hung2019-08-281-174/+5
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| * \ \ \ Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-284-88/+456
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| * | | | | CleanupEddie Hung2019-08-231-130/+59
| * | | | | Merge branch 'eddie/fix_techmap' into xaig_arrivalEddie Hung2019-08-201-1/+1
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| * | | | | | techmap -max_iter to apply to each module individuallyEddie Hung2019-08-201-4/+6
| * | | | | | Remove sequential extensionEddie Hung2019-08-201-68/+20
| * | | | | | retime_mode -> dff_modeEddie Hung2019-08-201-7/+7
| * | | | | | Fix use of {CLK,EN}_POLARITY, also add a FIXMEEddie Hung2019-08-201-65/+13
| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-201-6/+6
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| * \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-191-1/+1
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| * | | | | | | | Remove debugEddie Hung2019-08-191-1/+1
| * | | | | | | | Add (* abc_arrival *) attributeEddie Hung2019-08-191-1/+1
| * | | | | | | | Move from cell attr to module attrEddie Hung2019-08-191-24/+64
| * | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-1920-263/+263
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| * | | | | | | | | Use attributes instead of paramsEddie Hung2019-08-191-11/+25
| * | | | | | | | | Set abc_flop and use it in toposortEddie Hung2019-08-191-31/+51
| * | | | | | | | | Merge branch 'eddie/abc9_refactor' into xaig_dffEddie Hung2019-08-1627-1267/+1501
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| * | | | | | | | | | Error out if abc9 not called with -lut or -lutsEddie Hung2019-07-111-0/+3
| * | | | | | | | | | Count $_NOT_ cells turned into $lutsEddie Hung2019-07-111-7/+2
| * | | | | | | | | | WIP for fixing partitioning, temporarily do not partitionEddie Hung2019-07-111-12/+34
| * | | | | | | | | | write_verilog with *.v extensionEddie Hung2019-07-101-1/+1
| * | | | | | | | | | Remove -retime from abc9, revert to abc behav with separate clock/en domainsEddie Hung2019-07-101-29/+61
| * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-07-102-8/+22
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| * | | | | | | | | | | Also remove $__ABC_FF_Eddie Hung2019-07-011-1/+1
| * | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-07-014-91/+232
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| * | | | | | | | | | | | CleanupEddie Hung2019-06-171-3/+3
| * | | | | | | | | | | | Merge branch 'xaig' into xaig_dffEddie Hung2019-06-171-1/+1
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| * \ \ \ \ \ \ \ \ \ \ \ \ Merge branch 'xaig' into xaig_dffEddie Hung2019-06-171-3/+4
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| * \ \ \ \ \ \ \ \ \ \ \ \ \ Merge branch 'xaig' into xaig_dffEddie Hung2019-06-171-23/+26
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| * \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/xaig' into xaig_dffEddie Hung2019-06-171-1/+1
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| * | | | | | | | | | | | | | | | CleanupEddie Hung2019-06-151-40/+7
| * | | | | | | | | | | | | | | | abc9 to recover_init by defaultEddie Hung2019-06-151-11/+6
| * | | | | | | | | | | | | | | | Do not treat $__ABC_FF_ as a user cellEddie Hung2019-06-151-21/+6
| * | | | | | | | | | | | | | | | CleanupEddie Hung2019-06-151-10/+7
| * | | | | | | | | | | | | | | | Use $__ABC_FF_ instead of $_FF_Eddie Hung2019-06-151-13/+21
| * | | | | | | | | | | | | | | | Fix initialisation of flopsEddie Hung2019-06-151-2/+3
| * | | | | | | | | | | | | | | | Map to $_FF_ instead of $_DFF_P_ to prevent recursion issuesEddie Hung2019-06-151-13/+13
| * | | | | | | | | | | | | | | | For now, short $_DFF_[NP]_ from ff_map.v at re-integrationEddie Hung2019-06-151-0/+8
* | | | | | | | | | | | | | | | | Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes ...Clifford Wolf2019-09-051-8/+24
* | | | | | | | | | | | | | | | | Add flatten handling of pre-existing wires as created by interfaces, fixes #1145Clifford Wolf2019-09-051-8/+20
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* | | | | | | | | | | | | | | | Merge pull request #1340 from YosysHQ/eddie/abc_no_cleanEddie Hung2019-08-301-16/+10
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