diff options
author | Eddie Hung <eddie@fpgeh.com> | 2019-07-11 09:55:14 -0700 |
---|---|---|
committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-11 09:55:14 -0700 |
commit | 0c3ed73dade2488d0add1a3e6e82b148171f2d66 (patch) | |
tree | db7e62f33b494a0fb67207dab69ee3c80d3d9242 /passes/techmap | |
parent | 33862d04451ba58ce2b51c1e11abf86b65c3f018 (diff) | |
download | yosys-0c3ed73dade2488d0add1a3e6e82b148171f2d66.tar.gz yosys-0c3ed73dade2488d0add1a3e6e82b148171f2d66.tar.bz2 yosys-0c3ed73dade2488d0add1a3e6e82b148171f2d66.zip |
Count $_NOT_ cells turned into $luts
Diffstat (limited to 'passes/techmap')
-rw-r--r-- | passes/techmap/abc9.cc | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 4347c3789..53b0b8bbe 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -584,7 +584,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri log_assert(wire); module->connect(RTLIL::SigBit(wire, y_bit.offset), RTLIL::S1); } - else if (!lut_costs.empty() || !lut_file.empty()) { + else { RTLIL::Cell* driving_lut = nullptr; // ABC can return NOT gates that drive POs if (!a_bit.wire->port_input) { @@ -622,12 +622,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset), driver_lut); } - } - else { - cell = module->addCell(remap_name(c->name), "$_NOT_"); - cell->setPort("\\A", RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset)); - cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset)); - cell_stats[RTLIL::unescape_id(c->type)]++; + cell_stats["$lut"]++; } if (cell && markgroups) cell->attributes["\\abcgroup"] = map_autoidx; continue; |