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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 12:28:35 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 12:28:35 -0700 |
commit | c7f1ccbcb0b36093f619bbbd3c5dd621161134de (patch) | |
tree | f36d0aeaba4154117417b1dc55475c4dbe6cb362 /passes/techmap | |
parent | d87a6f6303194e2af0f9766185fa491077709a7b (diff) | |
parent | 999fb33fd0e6d1714bc61f7e50a5c16e0da9d4ab (diff) | |
download | yosys-c7f1ccbcb0b36093f619bbbd3c5dd621161134de.tar.gz yosys-c7f1ccbcb0b36093f619bbbd3c5dd621161134de.tar.bz2 yosys-c7f1ccbcb0b36093f619bbbd3c5dd621161134de.zip |
Merge remote-tracking branch 'origin/master' into xaig_arrival
Diffstat (limited to 'passes/techmap')
-rw-r--r-- | passes/techmap/abc9.cc | 26 |
1 files changed, 10 insertions, 16 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 11fe9c4a5..7eac08d17 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -668,30 +668,27 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri int in_wires = 0, out_wires = 0; // Stitch in mapped_mod's inputs/outputs into module - for (auto &it : mapped_mod->wires_) { - RTLIL::Wire *w = it.second; - if (!w->port_input && !w->port_output) - continue; - RTLIL::Wire *wire = module->wire(w->name); + for (auto port : mapped_mod->ports) { + RTLIL::Wire *w = mapped_mod->wire(port); + RTLIL::Wire *wire = module->wire(port); log_assert(wire); - RTLIL::Wire *remap_wire = module->wire(remap_name(w->name)); + RTLIL::Wire *remap_wire = module->wire(remap_name(port)); RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire)); log_assert(GetSize(signal) >= GetSize(remap_wire)); - log_assert(w->port_input || w->port_output); RTLIL::SigSig conn; - if (w->port_input) { - conn.first = remap_wire; - conn.second = signal; - in_wires++; - module->connect(conn); - } if (w->port_output) { conn.first = signal; conn.second = remap_wire; out_wires++; module->connect(conn); } + else if (w->port_input) { + conn.first = remap_wire; + conn.second = signal; + in_wires++; + module->connect(conn); + } } for (auto &it : bit_users) @@ -1274,9 +1271,6 @@ struct Abc9Pass : public Pass { assign_map.clear(); - // The "clean" pass also contains a design->check() call - Pass::call(design, "clean"); - log_pop(); } } Abc9Pass; |