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* Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fixClaire Wolf2020-03-261-1/+1
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| * techmap: Fix cell names with _TECHMAP_REPLACE_.*Marcin Koƛcielnicki2020-03-231-1/+1
* | iopadmap: Attempt to give new wires/cells meaningful namesR. Ou2020-03-221-6/+18
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* Merge pull request #1743 from YosysHQ/eddie/abc9_keepEddie Hung2020-03-112-13/+15
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| * abc9: for sccs, create a new wire instead of using entirety of existingEddie Hung2020-03-061-7/+7
| * abc9: (* keep *) wires to be PO only, not PI as well; fix scc handlingEddie Hung2020-03-061-8/+5
| * abc: add abc.debug scratchpad optionEddie Hung2020-03-061-0/+5
* | Merge pull request #1753 from YosysHQ/dave/abc9-speedupDavid Shah2020-03-101-7/+7
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| * | Add ScriptPass::run_nocheck and use for abc9David Shah2020-03-091-7/+7
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* | Merge pull request #1721 from YosysHQ/dave/tribuf-unusedDavid Shah2020-03-101-2/+1
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| * deminout: Don't demote inouts with unused bitsDavid Shah2020-03-041-2/+1
* | iopadmap: Look harder for already-present buffers. (#1731)Marcelina Koƛcielnicka2020-03-021-14/+54
* | Fixes for older compilersEddie Hung2020-02-271-1/+1
* | abc9_ops: suppress -prep_box warning for abc9_flopEddie Hung2020-02-271-1/+1
* | Make TimingInfo::TimingInfo(SigBit) constructor explicitEddie Hung2020-02-271-3/+3
* | TimingInfo: index by (port_name,offset)Eddie Hung2020-02-271-3/+4
* | Fix spacingEddie Hung2020-02-271-18/+18
* | abc9_ops: still emit delay table even box has no timingEddie Hung2020-02-271-3/+1
* | abc9_ops: demote lack of box timing info to warningEddie Hung2020-02-271-2/+4
* | Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-271-89/+15
* | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-24/+18
* | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-72/+53
* | abc9_ops: add and use new TimingInfo structEddie Hung2020-02-271-70/+41
* | abc9_ops: ignore (* abc9_flop *) if not '-dff'Eddie Hung2020-02-272-64/+64
* | abc9_ops: sort LUT delays to be ascendingEddie Hung2020-02-271-1/+4
* | abc9_ops: output LUT areaEddie Hung2020-02-271-6/+6
* | abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto-gen small LUTsEddie Hung2020-02-271-18/+33
* | xilinx: improve specify functionalityEddie Hung2020-02-271-19/+19
* | xilinx: use specify blocks in place of abc9_{arrival,required}Eddie Hung2020-02-271-158/+264
* | Auto-generate .box/.lut files from specify blocksEddie Hung2020-02-271-40/+117
* | abc9_ops: assert on $specify2 propertiesEddie Hung2020-02-271-0/+3
* | abc9_ops: -prep_box, to be called onceEddie Hung2020-02-272-50/+49
* | abc9_ops: -prep_lut and -write_lut to auto-generate LUT libraryEddie Hung2020-02-272-6/+115
* | Merge pull request #1709 from rqou/coolrunner2_counterClaire Wolf2020-02-271-97/+354
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| * extract_counter: Implement extracting up countersR. Ou2020-02-171-65/+247
| * extract_counter: Add support for inverted clock enableR. Ou2020-02-171-8/+28
| * extract_counter: Fix clock enableR. Ou2020-02-171-1/+3
| * extract_counter: Fix outputting count to module portR. Ou2020-02-171-8/+20
| * extract_counter: Allow forbidding async resetR. Ou2020-02-171-2/+17
| * extract_counter: Refactor out extraction settings into structR. Ou2020-02-171-17/+43
* | Closes #1714. Fix make failure when NDEBUG=1.Alberto Gonzalez2020-02-221-2/+0
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* Revert "abc9: fix abc9_arrival for flops"Eddie Hung2020-02-141-31/+2
* Merge pull request #1700 from YosysHQ/eddie/abc9_fixesEddie Hung2020-02-131-15/+33
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| * abc9: fix abc9_arrival for flopsEddie Hung2020-02-131-2/+31
| * abc9: deprecate abc9_ff.init wire for (* abc9_init *) attrEddie Hung2020-02-131-13/+2
* | iopadmap: fixes as suggested by @mwkmwkmwkEddie Hung2020-02-131-19/+11
* | iopadmap: move \init attributes from outpad output to its inputEddie Hung2020-02-131-3/+20
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* abc9: cleanupEddie Hung2020-02-101-1/+1
* Fix misc.abc9.abc9_abc9_lutsEddie Hung2020-02-071-1/+1
* abc9_ops: -reintegrate to use derived_type for box_portsEddie Hung2020-02-051-1/+1