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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-14 13:53:28 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | d6cff777513ff5b470bcd37588c123e118ad0cdb (patch) | |
| tree | b0d06b8c203c44ed363f4706c28483ec8cf93771 /passes/techmap | |
| parent | 5ff60d2057992bdc9f0ff04eee78d7bf6be0ee44 (diff) | |
| download | yosys-d6cff777513ff5b470bcd37588c123e118ad0cdb.tar.gz yosys-d6cff777513ff5b470bcd37588c123e118ad0cdb.tar.bz2 yosys-d6cff777513ff5b470bcd37588c123e118ad0cdb.zip | |
abc9_ops: still emit delay table even box has no timing
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index fc2f52157..8337b61b1 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -669,10 +669,8 @@ void prep_box(RTLIL::Design *design, bool dff_mode) ss << std::endl; auto &t = timing.setup_module(module).comb; - if (t.empty()) { + if (t.empty()) log_warning("(* abc9_box *) module '%s' has no timing (and thus no connectivity) information.\n", log_id(module)); - continue; - } for (const auto &o : outputs) { first = true; |