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authorEddie Hung <eddie@fpgeh.com>2020-03-06 10:30:07 -0800
committerEddie Hung <eddie@fpgeh.com>2020-03-06 10:30:07 -0800
commit80dcc8a0d1b6833f093c4ad6742c60187d1c9c00 (patch)
tree0ef8f81a008d50752444a0a678ebd34d87286a37 /passes/techmap
parent91a7a74ac438ba5b030d90fcfafeb1db03757d91 (diff)
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abc9: for sccs, create a new wire instead of using entirety of existing
Diffstat (limited to 'passes/techmap')
-rw-r--r--passes/techmap/abc9_ops.cc14
1 files changed, 7 insertions, 7 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 27e9fd239..e1baf4e3d 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -93,9 +93,10 @@ void check(RTLIL::Design *design)
void mark_scc(RTLIL::Module *module)
{
// For every unique SCC found, (arbitrarily) find the first
- // cell in the component, and convert all wires driven by
- // its output ports into a new PO, and drive its previous
- // sinks with a new PI
+ // cell in the component, and replace its output connections
+ // with a new wire driven by the old connection but with a
+ // special (* abc9_scc *) attribute set (which is used by
+ // write_xaiger to break this wire into PI and POs)
pool<RTLIL::Const> ids_seen;
for (auto cell : module->cells()) {
auto it = cell->attributes.find(ID(abc9_scc_id));
@@ -109,11 +110,10 @@ void mark_scc(RTLIL::Module *module)
for (auto &c : cell->connections_) {
if (c.second.is_fully_const()) continue;
if (cell->output(c.first)) {
- SigBit b = c.second.as_bit();
- // TODO: Don't be as heavy handed as to
- // mark the entire wire as part of the scc
- Wire *w = b.wire;
+ Wire *w = module->addWire(NEW_ID, GetSize(c.second));
w->set_bool_attribute(ID(abc9_scc));
+ module->connect(w, c.second);
+ c.second = w;
}
}
}