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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-12 15:33:02 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 12:33:58 -0800 |
| commit | 00d41905df74fd8bbfc5950c4c1ecf2d38394eaf (patch) | |
| tree | b65d01a24aac15190fdf73000d7e57238733fd11 /passes/techmap | |
| parent | cb7bc6a12fee1d948b7f91fd37f326dbd4f5ca47 (diff) | |
| download | yosys-00d41905df74fd8bbfc5950c4c1ecf2d38394eaf.tar.gz yosys-00d41905df74fd8bbfc5950c4c1ecf2d38394eaf.tar.bz2 yosys-00d41905df74fd8bbfc5950c4c1ecf2d38394eaf.zip | |
abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 15 |
1 files changed, 2 insertions, 13 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 7071f0de4..8f5718411 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -192,20 +192,9 @@ void prep_dff(RTLIL::Module *module) clkdomain_t key(abc9_clock); auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1)); - auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second)); - log_assert(r2.second); - - Wire *abc9_init_wire = module->wire(stringf("%s.init", cell->name.c_str())); - if (abc9_init_wire == NULL) - log_error("'%s.init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module)); - log_assert(GetSize(abc9_init_wire) == 1); - SigSpec abc9_init = assign_map(abc9_init_wire); - if (!abc9_init.is_fully_const()) - log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module)); - if (abc9_init == State::S1) - log_error("'%s.init' in module '%s' has value 1'b1 which is not supported by 'abc9 -dff'.\n", cell->name.c_str(), log_id(module)); - r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const())); + auto r2 = cell->attributes.insert(ID(abc9_mergeability));; log_assert(r2.second); + r2.first->second = r.first->second; } RTLIL::Module *holes_module = design->module(stringf("%s$holes", module->name.c_str())); |