iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	1	-1/+1
*	Fixes in old SAT example.ys	Clifford Wolf	2014-09-01	1	-3/+4
*	Moved "share" and "wreduce" to passes/opt/	Clifford Wolf	2014-09-01	2	-988/+0
*	azonenberg: Make dump_vcd save model when temporal induction fails due to ste...	Clifford Wolf	2014-08-24	1	-0/+2
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-2/+2
*	Fixed "share" for complex scenarios with never-active cells	Clifford Wolf	2014-08-09	1	-6/+22
*	Do not share any $reduce_* cells (its complicated and not worth it anyways)	Clifford Wolf	2014-08-09	1	-19/+0
*	Fixed sharing of reduce operator	Clifford Wolf	2014-08-08	1	-0/+13
*	Added "sat -prove-skip"	Clifford Wolf	2014-08-08	1	-2/+16
*	Use "-keepdc" in "miter -equiv -flatten"	Clifford Wolf	2014-08-07	1	-2/+2
*	Fixed "share" for memory read ports	Clifford Wolf	2014-08-03	1	-0/+7
*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02	1	-1/+1
*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	1	-3/+3
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	4	-31/+31
*	Renamed modwalker.h to modtools.h	Clifford Wolf	2014-07-31	1	-5/+6
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	4	-97/+97
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	1	-1/+1
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+1
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	6	-21/+21
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	5	-14/+14
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	5	-34/+34
*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-42/+13
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-18/+5
*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26	1	-1/+1
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-2/+2
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	4	-12/+21
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	5	-116/+116
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	5	-116/+116
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	4	-65/+20
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	3	-13/+5
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	2	-10/+4
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-8/+6
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	3	-8/+8
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	3	-8/+8
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3	Clifford Wolf	2014-07-23	1	-4/+4
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-2/+2
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	6	-84/+84
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	6	-84/+84
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	3	-21/+21
*	Wider range of cell types supported in "share" pass	Clifford Wolf	2014-07-21	1	-17/+197
*	Use ezSAT::non_incremental() in "share" pass	Clifford Wolf	2014-07-21	1	-0/+2
*	Added support for resource sharing in mux control logic	Clifford Wolf	2014-07-20	1	-86/+155
*	Supercell creation for $div/$mod worked all along, fixed test benches	Clifford Wolf	2014-07-20	1	-4/+0
*	Fixed creation of shift supercells in "share" pass	Clifford Wolf	2014-07-20	1	-4/+20
*	Added "miter -equiv -flatten"	Clifford Wolf	2014-07-20	1	-0/+14
*	Added "share" supercell creation	Clifford Wolf	2014-07-20	1	-1/+115
*	Added removing of always inactive cells to "share" pass	Clifford Wolf	2014-07-20	1	-8/+42
*	Progress in "share" pass	Clifford Wolf	2014-07-20	1	-112/+185
*	Progress in "share" pass	Clifford Wolf	2014-07-20	1	-19/+56
*	Started to implement real resource sharing	Clifford Wolf	2014-07-19	2	-0/+444