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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-265-116/+116
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-265-116/+116
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-254-65/+20
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-233-13/+5
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-232-10/+4
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-231-8/+6
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-233-8/+8
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-233-8/+8
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3Clifford Wolf2014-07-231-4/+4
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-221-2/+2
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-226-84/+84
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-226-84/+84
* Removed deprecated module->new_wire()Clifford Wolf2014-07-213-21/+21
* Wider range of cell types supported in "share" passClifford Wolf2014-07-211-17/+197
* Use ezSAT::non_incremental() in "share" passClifford Wolf2014-07-211-0/+2
* Added support for resource sharing in mux control logicClifford Wolf2014-07-201-86/+155
* Supercell creation for $div/$mod worked all along, fixed test benchesClifford Wolf2014-07-201-4/+0
* Fixed creation of shift supercells in "share" passClifford Wolf2014-07-201-4/+20
* Added "miter -equiv -flatten"Clifford Wolf2014-07-201-0/+14
* Added "share" supercell creationClifford Wolf2014-07-201-1/+115
* Added removing of always inactive cells to "share" passClifford Wolf2014-07-201-8/+42
* Progress in "share" passClifford Wolf2014-07-201-112/+185
* Progress in "share" passClifford Wolf2014-07-201-19/+56
* Started to implement real resource sharingClifford Wolf2014-07-192-0/+444
* now ignore init attributes on non-register wires in sat commandClifford Wolf2014-07-051-4/+24
* added log_header to miter and expose pass, show cell type for exposed portsJohann Glaser2014-05-282-3/+9
* Small improvement in SAT log messagesClifford Wolf2014-03-131-3/+3
* Fixed bug in freduce commandClifford Wolf2014-03-071-0/+30
* Some minor code cleanups in freduce commandClifford Wolf2014-03-071-5/+5
* Added freduce -dumpClifford Wolf2014-03-061-1/+24
* Added freduce -stopClifford Wolf2014-03-061-3/+18
* fixed freduce for Minisat::SimpSolver: use frozen_literal()Clifford Wolf2014-03-031-2/+2
* Added "sat -dump_cnf"Clifford Wolf2014-02-181-5/+34
* Coding style corrections in SatHelper::dump_model_to_vcd()Clifford Wolf2014-02-181-31/+31
* Added "sat -initsteps"Clifford Wolf2014-02-181-14/+29
* Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanupsClifford Wolf2014-02-171-5/+9
* Added "-dump_fail_to_vcd" argument to SAT solverAndrew Zonenberg2014-02-171-0/+114
* Various improvements in expose command (added -sep and -cut)Clifford Wolf2014-02-091-36/+119
* Fixed handling of async reset in expose -evert-dffClifford Wolf2014-02-081-0/+1
* Implemented expose -evert-dffClifford Wolf2014-02-081-11/+301
* Added generic RTLIL::SigSpec::parse_sel() with support for selection variablesClifford Wolf2014-02-062-34/+17
* Added support for sat -show @<sel_name>Clifford Wolf2014-02-061-0/+17
* Added sat -set-init-def and sat -tempinduct-defClifford Wolf2014-02-061-4/+34
* Added expose -dffClifford Wolf2014-02-061-1/+44
* Added miter -make_outcmpClifford Wolf2014-02-061-2/+23
* Added sat -set-init-zero supportClifford Wolf2014-02-061-2/+22
* Added sat -verify and -falsify support for non-prove casesClifford Wolf2014-02-061-14/+26
* Added expose commandClifford Wolf2014-02-052-0/+264
* added sat -falsifyClifford Wolf2014-02-041-4/+28
* Fixed bug in sequential sat proofs and improved handling of assertsClifford Wolf2014-02-041-2/+27