diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-07-05 11:17:40 +0200 |
---|---|---|
committer | Clifford Wolf <clifford@clifford.at> | 2014-07-05 11:18:38 +0200 |
commit | 3b52121d328d45a5d4269fd0e8de9af948c0216e (patch) | |
tree | 59d61572353b98e449d72f4802c4e7c164f7b5eb /passes/sat | |
parent | ee8ad72fd950e1ee204e5c97155a50b8b1445dec (diff) | |
download | yosys-3b52121d328d45a5d4269fd0e8de9af948c0216e.tar.gz yosys-3b52121d328d45a5d4269fd0e8de9af948c0216e.tar.bz2 yosys-3b52121d328d45a5d4269fd0e8de9af948c0216e.zip |
now ignore init attributes on non-register wires in sat command
Diffstat (limited to 'passes/sat')
-rw-r--r-- | passes/sat/sat.cc | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 87bff4c48..a9a00d8a2 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -103,10 +103,30 @@ struct SatHelper RTLIL::SigSpec rhs = it.second->attributes.at("\\init"); log_assert(lhs.width == rhs.width); - log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs)); - big_lhs.remove2(lhs, &big_rhs); - big_lhs.append(lhs); - big_rhs.append(rhs); + RTLIL::SigSpec removed_bits; + for (int i = 0; i < lhs.width; i++) { + RTLIL::SigSpec bit = lhs.extract(i, 1); + if (!satgen.initial_state.check_all(bit)) { + removed_bits.append(bit); + lhs.remove(i, 1); + rhs.remove(i, 1); + i--; + } + } + + lhs.optimize(); + rhs.optimize(); + removed_bits.optimize(); + + if (removed_bits.width) + log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits)); + + if (lhs.width) { + log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs)); + big_lhs.remove2(lhs, &big_rhs); + big_lhs.append(lhs); + big_rhs.append(rhs); + } } for (auto &s : sets_init) |