Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Rst docs conversion (#3496) | KrystalDelusion | 2022-11-15 | 1 | -1/+1 |
| | | | Rst docs conversion | ||||
* | sim: Run a comb-only update step to set past values during FST cosim | Jannis Harder | 2022-11-07 | 1 | -12/+11 |
| | | | | | | | | The previous approach only initialized past_d and past_ad while for FST cosim we also need to initialize the other past values like past_clk, etc. Also to properly initialize them, we need to run a combinational update step in case any of the wires feeding into the FF are private or otherwise not part of the FST. | ||||
* | Add extra time at the end of a sat VCD trace | Claire Xenia Wolf | 2022-11-01 | 1 | -0/+1 |
| | | | | | | | Otherwise the final values will not show up in gtkwave waveforms when looking at the generated traces. Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | ||||
* | Add miter -cross option | Claire Xenia Wolf | 2022-10-24 | 1 | -4/+32 |
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* | clk2fflogic: Always correctly handle simultaneously changing signals | Jannis Harder | 2022-10-07 | 1 | -103/+87 |
| | | | | | | | | | | | | | | | | | | | | | | | | This is a complete rewrite of the FF replacing code. The previous implementation tried to implement the negative hold time by wrapping async control signals individually with pulse stretching. This did not correctly model the interaction between different simultaneously changing inputs (e.g. a falling ALOAD together with a changing AD would load the changed AD instead of the value AD had when ALOAD was high; a falling CLR could mask a raising SET for one cycle; etc.). The new approach first has the logic for all updates using only sampled values followed by the logic for all updates using only current values. That way, e.g., a falling ALOAD will load the sampled AD value but a still active ALOAD will load the current AD value. The new code also has deterministic behavior for the initial state: no operation is active when that operation would depend on a specific previous signal value. This also means clk2fflogic will no longer generate any additional uninitialized FFs. I also documented the negative hold time behavior in the help message, copying the relevant part from async2sync's help messages. | ||||
* | mutate: warn if less mutations possible than number requested | N. Engelhardt | 2022-10-05 | 1 | -0/+2 |
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* | Fitting help messages to 80 character width | KrystalDelusion | 2022-08-24 | 2 | -24/+28 |
| | | | | | | | | | Uses the regex below to search (using vscode): ^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\); Finds any log messages double indented (which help messages are) and checks if *either* there are is no newline character at the end, *or* the number of characters before the newline is more than 80. | ||||
* | sim: -hdlname option to preserve flattened hierarchy in sim output | Jannis Harder | 2022-08-16 | 1 | -9/+41 |
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* | clk2fflogic: Generate less unused logic when using verific | Jannis Harder | 2022-08-16 | 1 | -1/+4 |
| | | | | | | Verific generates a lot of FFs with an unused async load and we cannot always optimize that away before running clk2fflogic, so check for that special case here. | ||||
* | formalff: New -setundef option | Jannis Harder | 2022-08-16 | 1 | -0/+335 |
| | | | | | | | Find FFs with undefined initialization values for which changing the initialization does not change the observable behavior and initialize them. For -ff2anyinit, this reduces the number of generated $anyinit cells that drive wires with private names. | ||||
* | formalff: Set new replaced_by_gclk attribute on removed dff's clks | Jannis Harder | 2022-08-16 | 1 | -0/+22 |
| | | | | | | This attribute can be used by formal backends to indicate which clocks were mapped to the global clock. Update the btor and smt2 backend which already handle clock inputs to understand this attribute. | ||||
* | Add the $anyinit cell and the formalff pass | Jannis Harder | 2022-08-16 | 3 | -1/+194 |
| | | | | | | | These can be used to protect undefined flip-flop initialization values from optimizations that are not sound for formal verification and can help mapping all solver-provided values in witness traces for flows that use different backends simultaneously. | ||||
* | support file locations containing spaces | Miodrag Milanovic | 2022-08-08 | 1 | -1/+1 |
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* | sim: Fix $anyseq in nested modules | Jannis Harder | 2022-07-22 | 1 | -11/+21 |
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* | async2sync: turn FFs with const clks into gclk FFs with feedback | Jannis Harder | 2022-06-30 | 1 | -0/+3 |
| | | | | | | | | The formal backends do not support multiple clocks. This includes constant clocks. Constant clocks do appear in what isn't a proper multiclock design, for example when mapping not fully initialized ROMs. As converting FFs with constant clocks to FFs using the global is doable even in a single clock flow, make async2sync do this. | ||||
* | fmcombine: Add _gold/_gate suffix to memids | Jannis Harder | 2022-06-03 | 1 | -0/+3 |
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* | Observe $TMPDIR variable when creating tmp files | Mohamed A. Bamakhrama | 2022-05-27 | 1 | -1/+1 |
| | | | | | | | | | POSIX defines $TMPDIR as containing the pathname of the directory where programs can create temporary files. On most systems, this variable points to "/tmp". However, on some systems it can point to a different location. Without respecting this variable, yosys fails to run on such systems. Signed-off-by: Mohamed A. Bamakhrama <mohamed@alumni.tum.de> | ||||
* | fix crash when no fst input | Miodrag Milanovic | 2022-05-04 | 1 | -1/+2 |
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* | Start restoring memory state from VCD/FST | Miodrag Milanovic | 2022-05-04 | 1 | -2/+17 |
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* | AIM file could have gaps in or between inputs and inits | Miodrag Milanovic | 2022-05-02 | 1 | -3/+6 |
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* | Match $anyseq input if connected to public wire | Miodrag Milanovic | 2022-04-22 | 1 | -6/+12 |
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* | Treat $anyseq as input from FST | Miodrag Milanovic | 2022-04-22 | 1 | -0/+21 |
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* | Last sample from input does not represent change | Miodrag Milanovic | 2022-04-22 | 1 | -1/+2 |
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* | latches are always set to zero | Miodrag Milanovic | 2022-04-22 | 1 | -6/+1 |
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* | If not multiclock, output only on clock edges | Miodrag Milanovic | 2022-04-22 | 1 | -0/+18 |
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* | Set init state for all wires from FST and set past | Miodrag Milanovic | 2022-04-22 | 1 | -13/+12 |
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* | Fix multiclock for btor2 witness | Miodrag Milanovic | 2022-04-22 | 1 | -5/+9 |
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* | Fix reading aiw from other solvers | Miodrag Milanovic | 2022-04-15 | 1 | -2/+2 |
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* | Use wrap_async_control_gate if ff is fine | Miodrag Milanovic | 2022-04-08 | 1 | -9/+11 |
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* | Makefile: properly conditionalize features requiring compression. | Iris Johnson | 2022-04-07 | 1 | -0/+2 |
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* | past_ad initial value setting | Miodrag Milanovic | 2022-04-02 | 1 | -0/+3 |
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* | setInitState can be only one altering values | Miodrag Milanovic | 2022-04-02 | 1 | -4/+6 |
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* | Set past_d value for init state | Miodrag Milanovic | 2022-04-02 | 1 | -0/+2 |
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* | Set init values for wrapped async control signals | Miodrag Milanovic | 2022-04-01 | 1 | -0/+2 |
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* | Support memories in aiw and multiclock | Miodrag Milanovic | 2022-03-31 | 1 | -16/+86 |
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* | Proper SigBit forming in sim | Miodrag Milanovic | 2022-03-22 | 1 | -4/+4 |
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* | Proper SigBit forming in sim | Miodrag Milanovic | 2022-03-22 | 1 | -4/+4 |
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* | More verbose warnings | Miodrag Milanovic | 2022-03-18 | 1 | -5/+7 |
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* | Recognize registers and set initial state for them in tb | Miodrag Milanovic | 2022-03-16 | 1 | -6/+32 |
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* | Update sim help message. | Miodrag Milanovic | 2022-03-16 | 1 | -1/+2 |
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* | Added fst2tb pass for generating testbench | Miodrag Milanovic | 2022-03-14 | 1 | -0/+319 |
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* | Merge pull request #3229 from YosysHQ/micko/sim_date | Miodrag Milanović | 2022-03-11 | 1 | -7/+20 |
|\ | | | | | Add date parameter to enable full date/time and version info | ||||
| * | Add date parameter to enable full date/time and version info | Miodrag Milanovic | 2022-03-11 | 1 | -7/+20 |
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* | | Add "sim -q" option | Claire Xenia Wolf | 2022-03-11 | 1 | -8/+19 |
|/ | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | ||||
* | Small fix in "sim" help message | Claire Xenia Wolf | 2022-03-11 | 1 | -1/+1 |
| | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | ||||
* | FstData already do conversion to VCD | Miodrag Milanovic | 2022-03-11 | 1 | -1/+2 |
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* | Support cell name in btor witness file | Miodrag Milanovic | 2022-03-11 | 1 | -5/+14 |
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* | Proper write of memory data | Miodrag Milanovic | 2022-03-11 | 1 | -14/+13 |
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* | Start work on memory init | Miodrag Milanovic | 2022-03-09 | 1 | -9/+34 |
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* | Fixes and error check | Miodrag Milanovic | 2022-03-09 | 1 | -1/+5 |
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