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| author | KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com> | 2022-11-16 00:55:22 +1300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-11-15 12:55:22 +0100 |
| commit | a14dec79ebc85fae807684fa027d8098a16a4d34 (patch) | |
| tree | f05562ce671f452f6d29a90219cced0b37c1aae4 /passes/sat | |
| parent | 853f4bb3c695d9f5183ef5064ec4cf9cdd8b5300 (diff) | |
| download | yosys-a14dec79ebc85fae807684fa027d8098a16a4d34.tar.gz yosys-a14dec79ebc85fae807684fa027d8098a16a4d34.tar.bz2 yosys-a14dec79ebc85fae807684fa027d8098a16a4d34.zip | |
Rst docs conversion (#3496)
Rst docs conversion
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/sim.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 3ac431223..1cd1ebc71 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -2014,7 +2014,7 @@ struct SimPass : public Pass { log(" -r\n"); log(" read simulation results file\n"); log(" File formats supported: FST, VCD, AIW and WIT\n"); - log(" VCD support requires vcd2fst external tool to be present\n"); + log(" VCD support requires vcd2fst external tool to be present\n"); log("\n"); log(" -map <filename>\n"); log(" read file with port and latch symbols, needed for AIGER witness input\n"); |