iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Cleanup	Eddie Hung	2019-08-28	1	-4/+0
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*	No need to replace Q of slice since $shiftx is autoremove-d	Eddie Hung	2019-08-28	1	-1/+0
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*	More cleanup	Eddie Hung	2019-08-28	1	-9/+6
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*	Do not use default_params dict, hardcode default values, cleanup	Eddie Hung	2019-08-28	1	-16/+13
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*	Missing close bracket	Eddie Hung	2019-08-26	1	-1/+1
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*	Remove leftover header	Eddie Hung	2019-08-26	1	-1/+0
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*	Create new $__XILINX_SHREG_ cell for variable length too	Eddie Hung	2019-08-23	1	-31/+30
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*	Create new cell for fixed length SRL	Eddie Hung	2019-08-23	1	-14/+22
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*	Fix last_cell.D	Eddie Hung	2019-08-23	1	-2/+1
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*	Update doc	Eddie Hung	2019-08-23	1	-12/+19
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*	Remove (* init *) entry when consumed into SRL	Eddie Hung	2019-08-23	1	-2/+6
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*	Forgot to slice	Eddie Hung	2019-08-23	1	-1/+2
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*	xilinx_srl to use 'slice' features of pmgen for word level	Eddie Hung	2019-08-23	1	-16/+31
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*	Add doc	Eddie Hung	2019-08-22	1	-1/+14
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*	Add copyright	Eddie Hung	2019-08-22	1	-0/+1
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*	Remove output_bits	Eddie Hung	2019-08-22	1	-12/+1
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*	Forgot to set ud_variable.minlen	Eddie Hung	2019-08-22	1	-0/+1
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*	Do not run xilinx_srl_pm in fixed loop	Eddie Hung	2019-08-22	1	-28/+24
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*	Add comment	Eddie Hung	2019-08-21	1	-0/+4
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*	Add variable length support to xilinx_srl	Eddie Hung	2019-08-21	1	-12/+100
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*	Rename pattern to fixed	Eddie Hung	2019-08-21	1	-9/+9
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*	xilinx_srl to support FDRE and FDRE_1	Eddie Hung	2019-08-21	1	-6/+23
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*	Fix polarity of EN_POL	Eddie Hung	2019-08-21	1	-2/+2
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*	Add CLKPOL == 0	Eddie Hung	2019-08-21	1	-0/+2
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*	Reject if not minlen from inside pattern matcher	Eddie Hung	2019-08-21	1	-7/+9
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*	Add init support	Eddie Hung	2019-08-21	1	-2/+11
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*	Fix spacing	Eddie Hung	2019-08-21	1	-2/+2
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*	Initial progress on xilinx_srl	Eddie Hung	2019-08-21	1	-0/+115