| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Only pack out registers if \init is zero or x; then remove \init from PREG | Eddie Hung | 2019-09-10 | 1 | -0/+10 |
| * | Fix RSTP | Eddie Hung | 2019-09-10 | 1 | -1/+1 |
| * | Add support for RSTP | Eddie Hung | 2019-09-10 | 1 | -4/+12 |
| * | enpol -> cepol | Eddie Hung | 2019-09-10 | 1 | -11/+11 |
| * | Update help text | Eddie Hung | 2019-09-10 | 1 | -3/+3 |
| * | Update xilinx_dsp help text | Eddie Hung | 2019-09-10 | 1 | -3/+21 |
| * | Oops | Eddie Hung | 2019-09-09 | 1 | -0/+1 |
| * | Support subtraction as well | Eddie Hung | 2019-09-09 | 1 | -112/+123 |
| * | Support TWO24 | Eddie Hung | 2019-09-09 | 1 | -1/+59 |
| * | Refactor | Eddie Hung | 2019-09-09 | 1 | -33/+33 |
| * | Add initial USE_SIMD=FOUR12 support | Eddie Hung | 2019-09-09 | 1 | -0/+157 |
| * | Pack CREG | Eddie Hung | 2019-09-06 | 1 | -12/+41 |
| * | Perform D replacement properly | Eddie Hung | 2019-09-06 | 1 | -2/+11 |
| * | Add support for DREG | Eddie Hung | 2019-09-06 | 1 | -0/+13 |
| * | Fix enable polarity | Eddie Hung | 2019-09-06 | 1 | -2/+2 |
| * | Logging for ffAD | Eddie Hung | 2019-09-06 | 1 | -0/+3 |
| * | Add support for pre-adder and AD register | Eddie Hung | 2019-09-06 | 1 | -1/+30 |
| * | Sensitive to CEB CEM CEP polarity | Eddie Hung | 2019-09-05 | 1 | -5/+8 |
| * | ffAmuxAB -> ffAenpol | Eddie Hung | 2019-09-05 | 1 | -2/+3 |
| * | Do not check signedness of post-adder (assume taken care of by DSP) | Eddie Hung | 2019-09-05 | 1 | -2/+0 |
| * | Do not make ff[MP]mux semioptional, use sigmap | Eddie Hung | 2019-09-05 | 1 | -2/+5 |
| * | Add support for CEP | Eddie Hung | 2019-09-05 | 1 | -17/+16 |
| * | Add support for CEB, remove check on nusers | Eddie Hung | 2019-09-05 | 1 | -7/+12 |
| * | Support CEA | Eddie Hung | 2019-09-05 | 1 | -6/+11 |
| * | Get rid of sigBset too | Eddie Hung | 2019-09-04 | 1 | -4/+0 |
| * | Get rid of sigPused | Eddie Hung | 2019-09-04 | 1 | -2/+0 |
| * | Support CEM | Eddie Hung | 2019-09-04 | 1 | -4/+6 |
| * | st.ffP from if to assert | Eddie Hung | 2019-09-03 | 1 | -1/+2 |
| * | Rename muxAB to postAddMux | Eddie Hung | 2019-09-03 | 1 | -11/+11 |
| * | Use choices for addAB, now called postAdd | Eddie Hung | 2019-09-03 | 1 | -6/+6 |
| * | Add support for load value into DSP48E1.P | Eddie Hung | 2019-09-03 | 1 | -1/+6 |
| * | Process post-adder first since C could be used for load-P | Eddie Hung | 2019-09-03 | 1 | -18/+22 |
| * | Use feedback path for MACC | Eddie Hung | 2019-09-03 | 1 | -15/+21 |
| * | autoremove ffM | Eddie Hung | 2019-08-30 | 1 | -0/+1 |
| * | ffM before addAB | Eddie Hung | 2019-08-30 | 1 | -1/+1 |
| * | Another oops | Eddie Hung | 2019-08-30 | 1 | -1/+1 |
| * | Update commented out | Eddie Hung | 2019-08-30 | 1 | -1/+1 |
| * | Add support for ffM | Eddie Hung | 2019-08-30 | 1 | -0/+12 |
| * | Perform C -> PCIN optimisation after pattern matcher | Eddie Hung | 2019-08-13 | 1 | -10/+57 |
| * | Rename to XilinxDspPass | Eddie Hung | 2019-08-13 | 1 | -3/+3 |
| * | Pack partial-product adder DSP48E1 packing | Eddie Hung | 2019-08-09 | 1 | -5/+17 |
| * | Remove muxY and ffY for now | Eddie Hung | 2019-08-08 | 1 | -5/+5 |
| * | Disable $dffe | Eddie Hung | 2019-08-08 | 1 | -8/+8 |
| * | Pack P register properly | Eddie Hung | 2019-08-01 | 1 | -2/+4 |
| * | Fine tune ice40_dsp.pmg, add support for packing subsets of registers | Eddie Hung | 2019-07-19 | 1 | -1/+1 |
| * | Do not autoremove ffP aor muxP | Eddie Hung | 2019-07-18 | 1 | -2/+0 |
| * | Improve pattern matcher to match subsets of $dffe? cells | Eddie Hung | 2019-07-18 | 1 | -2/+8 |
| * | Improve A/B reg packing | Eddie Hung | 2019-07-18 | 1 | -0/+3 |
| * | Do not autoremove A/B registers since they might have other consumers | Eddie Hung | 2019-07-18 | 1 | -2/+0 |
| * | Pattern matcher to check pool of bits, not exactly | Eddie Hung | 2019-07-17 | 1 | -3/+9 |
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index : iCE40/yosys | |
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