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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-04 10:52:51 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-04 10:52:51 -0700 |
| commit | e67e4a5ed66df59f5f924e6bb3891f87fc93f070 (patch) | |
| tree | 4adee1660809a6cf88b014a8094ab16cadcda982 /passes/pmgen/xilinx_dsp.cc | |
| parent | 80aec0f006b91b0163c8be94f2450223e6e97a52 (diff) | |
| download | yosys-e67e4a5ed66df59f5f924e6bb3891f87fc93f070.tar.gz yosys-e67e4a5ed66df59f5f924e6bb3891f87fc93f070.tar.bz2 yosys-e67e4a5ed66df59f5f924e6bb3891f87fc93f070.zip | |
Support CEM
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 95105275b..4d2152f61 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -39,6 +39,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) log("ffB: %s\n", log_id(st.ffB, "--")); log("dsp: %s\n", log_id(st.dsp, "--")); log("ffM: %s\n", log_id(st.ffM, "--")); + log("ffMmux: %s\n", log_id(st.ffMmux, "--")); log("postAdd: %s\n", log_id(st.postAdd, "--")); log("postAddMux: %s\n", log_id(st.postAddMux, "--")); log("ffP: %s\n", log_id(st.ffP, "--")); @@ -111,11 +112,12 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) SigSpec Q = st.ffM->getPort("\\Q"); P.replace(pm.sigmap(D), Q); cell->setParam("\\MREG", State::S1); - if (st.ffM->type == "$dff") + if (st.ffMmux) { + cell->setPort("\\CEM", st.ffMmux->getPort("\\S")); + pm.autoremove(st.ffMmux); + } + else cell->setPort("\\CEM", State::S1); - //else if (st.ffP->type == "$dffe") - // cell->setPort("\\CEM", st.ffM->getPort("\\EN")); - else log_abort(); pm.autoremove(st.ffM); } if (st.ffP) { |