diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 15:53:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-03 15:53:10 -0700 |
| commit | 2d80866dafe9e2e2edd2d49e999c1f6a35541852 (patch) | |
| tree | 5e1b5c72e0a955bc3fc72e5b831545a319b423e1 /passes/pmgen/xilinx_dsp.cc | |
| parent | 682153de4bb1869187e567a41c22fbed23bcdfd1 (diff) | |
| download | yosys-2d80866dafe9e2e2edd2d49e999c1f6a35541852.tar.gz yosys-2d80866dafe9e2e2edd2d49e999c1f6a35541852.tar.bz2 yosys-2d80866dafe9e2e2edd2d49e999c1f6a35541852.zip | |
Add support for load value into DSP48E1.P
Diffstat (limited to 'passes/pmgen/xilinx_dsp.cc')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 1732a2d6a..b3d302071 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -40,6 +40,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) log("dsp: %s\n", log_id(st.dsp, "--")); log("ffM: %s\n", log_id(st.ffM, "--")); log("addAB: %s\n", log_id(st.addAB, "--")); + log("muxAB: %s\n", log_id(st.muxAB, "--")); log("ffP: %s\n", log_id(st.ffP, "--")); //log("muxP: %s\n", log_id(st.muxP, "--")); log("sigPused: %s\n", log_signal(st.sigPused)); @@ -58,7 +59,11 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) log(" adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type)); SigSpec &opmode = cell->connections_.at("\\OPMODE"); - if (st.ffP && C == P) { + if (st.ffP && st.muxAB) { + opmode[4] = st.muxAB->getPort("\\S"); + pm.autoremove(st.muxAB); + } + else if (st.ffP && C == P) { C = SigSpec(); opmode[4] = State::S0; } |