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* Improved TopoSort determinismClifford Wolf2014-11-072-4/+6
* Added "opt -full" alias for all more aggressive optimizationsClifford Wolf2014-10-313-7/+29
* Fixed various VS warningsClifford Wolf2014-10-182-3/+3
* Don't be too smart with $dff cells with "init" attribute on out signalClifford Wolf2014-10-161-1/+1
* Some cleanups in opt_cleanClifford Wolf2014-10-161-16/+9
* Wrapped init in std::set constructorWilliam Speirs2014-10-151-2/+2
* Do not the 'z' modifier in format string (another win32 fix)Clifford Wolf2014-10-111-2/+2
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-104-113/+113
* sat encoding for exclusive $pmux ctrl inputs in "share" passClifford Wolf2014-10-031-4/+16
* added resource sharing of $macc cellsClifford Wolf2014-10-031-3/+261
* Added $_BUF_ cell typeClifford Wolf2014-10-031-2/+2
* remove buffers in opt_cleanClifford Wolf2014-10-031-0/+13
* resource sharing of $alu cellsClifford Wolf2014-10-031-3/+21
* Added support for "keep" on modulesClifford Wolf2014-09-292-2/+2
* namespace YosysClifford Wolf2014-09-278-17/+45
* Re-enabled assert for new logic loops in "share" passClifford Wolf2014-09-211-4/+1
* Various improvements regarding logic loops in "share" resultsClifford Wolf2014-09-211-37/+108
* Logic loop bugfix for "share" passClifford Wolf2014-09-211-3/+7
* Added "share -limit"Clifford Wolf2014-09-211-1/+13
* Still loop bug in "share": changed assert to warningClifford Wolf2014-09-211-13/+25
* Do not introduce new logic loops in "share"Clifford Wolf2014-09-211-6/+47
* Assert on new logic loops in "share" passClifford Wolf2014-09-211-0/+48
* Fixed wreduce $shiftx handlingClifford Wolf2014-09-151-1/+1
* Cleanup in wreduceClifford Wolf2014-09-141-11/+8
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-2/+2
* Fixed "opt_const -fine" for $pos cellsClifford Wolf2014-09-041-9/+4
* Removed $bu0 cell typeClifford Wolf2014-09-043-10/+7
* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-013-0/+1342
* Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-011-1/+1
* Added design->scratchpadClifford Wolf2014-08-308-64/+19
* Optimize shift ops with constant rhs in opt_constClifford Wolf2014-08-241-0/+35
* Added some additional log messages to opt_constClifford Wolf2014-08-241-1/+10
* Renamed toposort.h to utils.hClifford Wolf2014-08-171-1/+1
* Added "opt -fast"Clifford Wolf2014-08-161-19/+45
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-6/+6
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-151-2/+2
* RIP $safe_pmuxClifford Wolf2014-08-143-3/+2
* Fixed a performance bug in opt_reduceClifford Wolf2014-08-021-2/+6
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-024-29/+30
* Replaced sha1 implementationClifford Wolf2014-08-012-7/+1
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-315-170/+170
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-291-7/+9
* Using log_assert() instead of assert()Clifford Wolf2014-07-285-7/+2
* Added SigPool::check(bit)Clifford Wolf2014-07-271-2/+2
* Fixed bug in opt_cleanClifford Wolf2014-07-271-1/+1
* Improved performance of opt_const on large modulesClifford Wolf2014-07-271-29/+54
* Fixed a bug in opt_clean and some RTLIL API usage cleanupsClifford Wolf2014-07-272-13/+14
* Using new obj iterator API in a few placesClifford Wolf2014-07-271-12/+11
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-276-7/+7
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-276-18/+18
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