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* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-028-322/+322
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* kernel: use more ID::*Eddie Hung2020-04-023-40/+40
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* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-021-8/+8
|\ | | | | kernel: speedup by using more pass-by-const-ref
| * kernel: SigSpec use more const& + overloads to prevent implicit SigSpecEddie Hung2020-03-131-8/+8
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* | memory_share: fix stray braceEddie Hung2020-03-301-1/+0
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* | Code review fixesEddie Hung2020-03-301-2/+2
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* | Apply suggestions from code reviewEddie Hung2020-03-301-4/+1
| | | | | | Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
* | kernel: share a single CellTypes within a passEddie Hung2020-03-181-4/+16
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* CleanupEddie Hung2019-12-171-11/+7
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* Enforce non-existenceEddie Hung2019-12-161-0/+4
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* Update docEddie Hung2019-12-161-4/+6
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* More sloppiness, thanks @dh73 for spottingEddie Hung2019-12-161-4/+4
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* OopsEddie Hung2019-12-161-4/+1
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* Implement 'attributes' grammarEddie Hung2019-12-161-80/+88
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* Fixing compiler warning/issues. Moving test script to the correct placeDiego H2019-12-161-8/+8
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* Merging attribute rules into a single match block; Adding testsDiego H2019-12-151-68/+80
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* Refactoring memory attribute matching based on IEEE 1364.1 and Tool specificDiego H2019-12-131-0/+77
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* Merge pull request #1501 from YosysHQ/dave/mem_copy_attrClifford Wolf2019-11-271-0/+4
|\ | | | | memory_collect: Copy attr from RTLIL::Memory to cell
| * memory_collect: Copy attr from RTLIL::Memory to cellDavid Shah2019-11-181-0/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Add "opt_mem" passClifford Wolf2019-11-221-0/+2
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* stoi -> atoiEddie Hung2019-08-071-4/+4
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* Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-061-4/+4
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* Use State::S{0,1}Eddie Hung2019-08-062-6/+6
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* Make liberal use of IdString.in()Eddie Hung2019-08-062-4/+4
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* Error out if enable > dbitsEddie Hung2019-07-131-0/+4
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* memory_dff: Fix checking of feedback mux input when more than one muxDavid Shah2019-07-021-3/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix spacingEddie Hung2019-06-251-4/+3
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* Move only one consumer check outside of while loopEddie Hung2019-06-251-6/+5
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* Walk through as many muxes as exist for rd_enEddie Hung2019-06-241-8/+16
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* memory_bram: Fix multiport make_transpDavid Shah2019-04-071-1/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* memory_bram: Consider read enable for address expansion registerDavid Shah2019-04-021-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* memory_bram: Reset make_transp when growing read portsDavid Shah2019-03-271-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* memory_bram: Fix multiclock make_transpDavid Shah2019-03-241-9/+16
| | | | Signed-off-by: David Shah <dave@ds0.me>
* memory_collect: do not truncate 'x from \INIT.whitequark2018-12-211-3/+0
| | | | | | | The semantics of an RTLIL constant that has less bits than its declared bit width is zero padding. Therefore, if the output of memory_collect will be used for simulation, truncating 'x from the end of \INIT will produce incorrect simulation results.
* memory_dff: Fix typo when checking init valueDavid Shah2018-12-181-1/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* memory_bram: Fix initdata bit order after shufflingGraham Edgecombe2018-12-111-0/+17
| | | | | | | | | | | | | In some cases the memory_bram pass shuffles the order of the bits in a memory's RD_DATA port. Although the order of the bits in the WR_DATA and WR_EN ports is changed to match the RD_DATA port, the order of the bits in the initialization data is not. This causes reads of initialized memories to return invalid data (until the initialization data is overwritten). This commit fixes the bug by shuffling the initdata bits in exactly the same order as the RD_DATA/WR_DATA/WR_EN bits.
* memory_bram: Reset make_outreg when growing read portsDavid Shah2018-10-191-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-209-18/+18
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Disable memory_dff for initialized FFsClifford Wolf2018-05-281-1/+19
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add some cleanup code to memory_nordffClifford Wolf2018-05-281-26/+36
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "memory_nordff" passClifford Wolf2018-03-062-0/+112
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Typo fix.Kaj Tuomi2016-09-081-1/+1
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* Fixed handling of transparent bram rd ports on ROMsClifford Wolf2016-08-271-0/+3
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* Fixed bug in memory_share for memory ports with different ABITSClifford Wolf2016-08-221-0/+6
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* Added memory_memx pass, "memory -memx", and "prep -memx"Clifford Wolf2016-08-193-2/+104
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* Optimize memory address port width in wreduce and memory_collect, not ↵Clifford Wolf2016-08-191-3/+13
| | | | verilog front-end
* Don't sign-extend memory bram initialization dataClifford Wolf2016-05-151-1/+1
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* Added "yosys -D" featureClifford Wolf2016-04-217-7/+7
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* Bugfix and improvements in memory_shareClifford Wolf2016-04-211-22/+19
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* Renamed opt_share to opt_mergeClifford Wolf2016-03-311-1/+1
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