iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed memory_unpack for initialized memories	Clifford Wolf	2015-04-29	1	-0/+17
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-2/+6
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-3/+3
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-7/+7
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-1/+1
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+0
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-2/+2
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-7/+7
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-7/+7
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-10/+3
*	Changes to "memory" pass for new $memwr/$mem WR_EN interface	Clifford Wolf	2014-07-16	1	-1/+1
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-0/+1
*	Added automatic memid generation to memory_unpack command	Clifford Wolf	2014-01-17	1	-2/+2
*	Added memory_unpack command	Clifford Wolf	2014-01-17	1	-0/+116