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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-02 13:11:01 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-02 13:19:57 +0200 |
| commit | b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3 (patch) | |
| tree | fa56668843c23b8d03a0652be802410f888c6384 /passes/memory/memory_unpack.cc | |
| parent | 14412e6c957a34381c33740426b35f7b90a446be (diff) | |
| download | yosys-b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3.tar.gz yosys-b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3.tar.bz2 yosys-b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3.zip | |
More cleanups related to RTLIL::IdString usage
Diffstat (limited to 'passes/memory/memory_unpack.cc')
| -rw-r--r-- | passes/memory/memory_unpack.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 68e9a9697..5a4c4eac9 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -31,7 +31,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at("\\MEMID").decode_string()); while (module->memories.count(mem_name) != 0) - mem_name += stringf("_%d", autoidx++); + mem_name = mem_name.str() + stringf("_%d", autoidx++); RTLIL::Memory *mem = new RTLIL::Memory; mem->name = mem_name; @@ -47,7 +47,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) for (int i = 0; i < num_rd_ports; i++) { RTLIL::Cell *cell = module->addCell(NEW_ID, "$memrd"); - cell->parameters["\\MEMID"] = mem_name; + cell->parameters["\\MEMID"] = mem_name.str(); cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS"); cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const(); @@ -61,7 +61,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) for (int i = 0; i < num_wr_ports; i++) { RTLIL::Cell *cell = module->addCell(NEW_ID, "$memwr"); - cell->parameters["\\MEMID"] = mem_name; + cell->parameters["\\MEMID"] = mem_name.str(); cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS"); cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const(); |