diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-16 12:13:13 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-16 12:49:50 +0200 |
| commit | 765f172211c8d7d8f14b6010193d8b53f5ec5e8f (patch) | |
| tree | 71de505f19b08ddc8ce2da23683f035e77672a20 /passes/memory/memory_unpack.cc | |
| parent | dcdd5c11b4ebbf983f3ab7fc5304d980cc47302d (diff) | |
| download | yosys-765f172211c8d7d8f14b6010193d8b53f5ec5e8f.tar.gz yosys-765f172211c8d7d8f14b6010193d8b53f5ec5e8f.tar.bz2 yosys-765f172211c8d7d8f14b6010193d8b53f5ec5e8f.zip | |
Changes to "memory" pass for new $memwr/$mem WR_EN interface
Diffstat (limited to 'passes/memory/memory_unpack.cc')
| -rw-r--r-- | passes/memory/memory_unpack.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 782c0cd79..bbd015833 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -74,7 +74,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const(); cell->parameters["\\PRIORITY"] = i; cell->connections["\\CLK"] = memory->connections.at("\\WR_CLK").extract(i, 1); - cell->connections["\\EN"] = memory->connections.at("\\WR_EN").extract(i, 1); + cell->connections["\\EN"] = memory->connections.at("\\WR_EN").extract(i*mem->width, mem->width); cell->connections["\\ADDR"] = memory->connections.at("\\WR_ADDR").extract(i*abits, abits); cell->connections["\\DATA"] = memory->connections.at("\\WR_DATA").extract(i*mem->width, mem->width); module->add(cell); |