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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-03 13:01:45 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-03 13:01:45 +0100 |
| commit | a6750b375301f2c2ebb51a2496cdf2c820b2546b (patch) | |
| tree | e3a91710abab3a7a89858426b0d17601946d8fec /passes/memory/memory_unpack.cc | |
| parent | de9226a64f96a3731008218727d6b3897c58f593 (diff) | |
| download | yosys-a6750b375301f2c2ebb51a2496cdf2c820b2546b.tar.gz yosys-a6750b375301f2c2ebb51a2496cdf2c820b2546b.tar.bz2 yosys-a6750b375301f2c2ebb51a2496cdf2c820b2546b.zip | |
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Diffstat (limited to 'passes/memory/memory_unpack.cc')
| -rw-r--r-- | passes/memory/memory_unpack.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 060d8e671..782c0cd79 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -55,6 +55,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const(); cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const(); + cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const(); cell->connections["\\CLK"] = memory->connections.at("\\RD_CLK").extract(i, 1); cell->connections["\\ADDR"] = memory->connections.at("\\RD_ADDR").extract(i*abits, abits); cell->connections["\\DATA"] = memory->connections.at("\\RD_DATA").extract(i*mem->width, mem->width); |