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* Clean up `passes/memory/memory_unpack.cc`.Alberto Gonzalez2020-04-091-7/+6
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-41/+41
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Added read-enable to memory modelClifford Wolf2015-09-251-0/+1
* Keep gcc from complaining about uninitialized variablesLarry Doolittle2015-08-141-1/+1
* Added WORDS parameter to $meminitClifford Wolf2015-07-311-7/+25
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Fixed memory_unpack for initialized memoriesClifford Wolf2015-04-291-0/+17
* namespace YosysClifford Wolf2014-09-271-2/+6
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-3/+3
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-7/+7
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-311-1/+1
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+0
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-2/+2
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-7/+7
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-7/+7
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-10/+3
* Changes to "memory" pass for new $memwr/$mem WR_EN interfaceClifford Wolf2014-07-161-1/+1
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-031-0/+1
* Added automatic memid generation to memory_unpack commandClifford Wolf2014-01-171-2/+2
* Added memory_unpack commandClifford Wolf2014-01-171-0/+116