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* Make liberal use of IdString.in()Eddie Hung2019-08-061-3/+3
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Typo fix.Kaj Tuomi2016-09-081-1/+1
* Fixed bug in memory_share for memory ports with different ABITSClifford Wolf2016-08-221-0/+6
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Bugfix and improvements in memory_shareClifford Wolf2016-04-211-22/+19
* Renamed opt_share to opt_mergeClifford Wolf2016-03-311-1/+1
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Fixed memory_share for unconditional write with part select to memoryClifford Wolf2015-04-221-0/+3
* Replaced ezDefaultSAT with ezSatPtrClifford Wolf2015-02-211-7/+7
* Added onehot attributeClifford Wolf2015-02-041-0/+13
* More dict/pool related changesClifford Wolf2014-12-271-2/+2
* namespace YosysClifford Wolf2014-09-271-2/+2
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-1/+1
* Added ModIndex helper class, some changes to RTLIL::MonitorClifford Wolf2014-08-011-3/+2
* Renamed modwalker.h to modtools.hClifford Wolf2014-07-311-5/+6
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-53/+53
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-291-0/+2
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-2/+2
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-13/+22
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-51/+51
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-51/+51
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-4/+2
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-2/+0
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-231-1/+1
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-231-1/+1
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-6/+6
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-6/+6
* Removed deprecated module->new_wire()Clifford Wolf2014-07-211-2/+2
* Improved memory_share log messagesClifford Wolf2014-07-191-3/+3
* More verbose memory_share help messageClifford Wolf2014-07-191-0/+17
* Added SAT-based write-port sharing to memory_shareClifford Wolf2014-07-191-0/+180
* Fixed bug in memory_share feedback-to-en codeClifford Wolf2014-07-191-4/+12
* Added translation from read-feedback to en-signals in memory_shareClifford Wolf2014-07-181-10/+236
* Only create collision detect logic in memory_share if necessaryClifford Wolf2014-07-181-4/+47
* Added memory_shareClifford Wolf2014-07-181-0/+263