iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Make liberal use of IdString.in()	Eddie Hung	2019-08-06	1	-3/+3
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Typo fix.	Kaj Tuomi	2016-09-08	1	-1/+1
*	Fixed bug in memory_share for memory ports with different ABITS	Clifford Wolf	2016-08-22	1	-0/+6
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Bugfix and improvements in memory_share	Clifford Wolf	2016-04-21	1	-22/+19
*	Renamed opt_share to opt_merge	Clifford Wolf	2016-03-31	1	-1/+1
*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	1	-1/+1
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Fixed memory_share for unconditional write with part select to memory	Clifford Wolf	2015-04-22	1	-0/+3
*	Replaced ezDefaultSAT with ezSatPtr	Clifford Wolf	2015-02-21	1	-7/+7
*	Added onehot attribute	Clifford Wolf	2015-02-04	1	-0/+13
*	More dict/pool related changes	Clifford Wolf	2014-12-27	1	-2/+2
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-2/+2
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	1	-1/+1
*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	1	-3/+2
*	Renamed modwalker.h to modtools.h	Clifford Wolf	2014-07-31	1	-5/+6
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-53/+53
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-0/+2
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-2/+2
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-13/+22
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-51/+51
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-51/+51
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-4/+2
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-2/+0
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-1/+1
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-1/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-6/+6
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-6/+6
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	1	-2/+2
*	Improved memory_share log messages	Clifford Wolf	2014-07-19	1	-3/+3
*	More verbose memory_share help message	Clifford Wolf	2014-07-19	1	-0/+17
*	Added SAT-based write-port sharing to memory_share	Clifford Wolf	2014-07-19	1	-0/+180
*	Fixed bug in memory_share feedback-to-en code	Clifford Wolf	2014-07-19	1	-4/+12
*	Added translation from read-feedback to en-signals in memory_share	Clifford Wolf	2014-07-18	1	-10/+236
*	Only create collision detect logic in memory_share if necessary	Clifford Wolf	2014-07-18	1	-4/+47
*	Added memory_share	Clifford Wolf	2014-07-18	1	-0/+263