| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | Added hierarchy -auto-top | Clifford Wolf | 2015-03-18 | 1 | -1/+33 |
| * | Fixed bug in "hierarchy" for parametric designs | Clifford Wolf | 2015-03-04 | 1 | -20/+19 |
| * | Cosmetic fixes in "hierarchy" for blackbox modules | Clifford Wolf | 2015-02-15 | 1 | -2/+4 |
| * | Fixed pattern matching in "hierarchy -generate" | Clifford Wolf | 2015-01-04 | 1 | -2/+2 |
| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -2/+2 |
| * | Fixed off-by-one bug in "hierarchy -check" for positional module args | Clifford Wolf | 2014-12-24 | 1 | -2/+2 |
| * | Checking existence of ports in "hierarchy -check" | Clifford Wolf | 2014-12-19 | 1 | -0/+13 |
| * | Fixed bug in "hierarchy -top" with array of instances | Clifford Wolf | 2014-11-27 | 1 | -3/+10 |
| * | Added log_warning() API | Clifford Wolf | 2014-11-09 | 1 | -2/+2 |
| * | Various win32 / vs build fixes | Clifford Wolf | 2014-10-17 | 1 | -2/+2 |
| * | Header changes so it will compile on VS | William Speirs | 2014-10-17 | 1 | -1/+5 |
| * | Do not the 'z' modifier in format string (another win32 fix) | Clifford Wolf | 2014-10-11 | 1 | -1/+1 |
| * | Moved patmatch() to yosys.cc | Clifford Wolf | 2014-10-10 | 1 | -1/+0 |
| * | Replaced fnmatch() with patmatch() | Clifford Wolf | 2014-10-10 | 1 | -5/+4 |
| * | set "keep" on modules with $assert cells in "hierarchy" | Clifford Wolf | 2014-09-30 | 1 | -0/+30 |
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 2 | -11/+17 |
| * | Corrected spelling mistakes found by lintian | Ruben Undheim | 2014-09-06 | 1 | -4/+4 |
| * | Added module->ports | Clifford Wolf | 2014-08-14 | 2 | -4/+5 |
| * | More bugfixes related to new RTLIL::IdString | Clifford Wolf | 2014-08-02 | 1 | -1/+1 |
| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 2 | -20/+20 |
| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -1/+1 |
| * | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 | 2 | -2/+2 |
| * | Allow "hierarchy -generate" for $__ cells | Clifford Wolf | 2014-07-29 | 1 | -1/+3 |
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 2 | -3/+3 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 2 | -36/+36 |
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 2 | -8/+8 |
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 2 | -5/+5 |
| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 2 | -21/+23 |
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 2 | -5/+5 |
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 2 | -11/+11 |
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 2 | -11/+11 |
| * | Added copy-constructor-like module->addCell(name, other) method | Clifford Wolf | 2014-07-26 | 1 | -4/+1 |
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -8/+6 |
| * | Fixed all users of SigSpec::chunks_rw() and removed it | Clifford Wolf | 2014-07-23 | 1 | -4/+4 |
| * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created... | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 2 | -4/+4 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 2 | -4/+4 |
| * | Added call_on_selection() and call_on_module() API | Clifford Wolf | 2014-07-20 | 1 | -1/+1 |
| * | fixed cell array handling of positional arguments | Clifford Wolf | 2014-06-07 | 1 | -2/+11 |
| * | Add support for cell arrays | Clifford Wolf | 2014-06-07 | 1 | -0/+34 |
| * | Implemented read_verilog -defer | Clifford Wolf | 2014-02-13 | 1 | -7/+19 |
| * | Moved some passes to other source directories | Clifford Wolf | 2014-02-08 | 2 | -0/+351 |
| * | Added hierarchy -purge_lib option | Clifford Wolf | 2014-02-04 | 1 | -3/+14 |
| * | Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3)) | Martin Schmölzer | 2014-01-14 | 1 | -0/+1 |
| * | Added hierarchy -libdir option | Clifford Wolf | 2014-01-14 | 1 | -4/+48 |
| * | Replaced signed_parameters API with CONST_FLAG_SIGNED | Clifford Wolf | 2013-12-04 | 1 | -1/+1 |
| * | Remove auto_wire framework (smarter than the verilog standard) | Clifford Wolf | 2013-11-24 | 1 | -60/+0 |
| * | Implemented correct handling of signed module parameters | Clifford Wolf | 2013-11-24 | 1 | -1/+1 |
| * | Added "top" attribute to mark top module in hierarchy | Clifford Wolf | 2013-11-24 | 1 | -0/+17 |
| * | Renamed "placeholder" to "blackbox" | Clifford Wolf | 2013-11-22 | 1 | -3/+3 |
