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* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-1/+1
* Added basic support for $expect cellsClifford Wolf2016-07-131-1/+1
* Made the expansion order of hierarchy deterministicMarcus Comstedt2016-05-221-3/+3
* Added "yosys -D" featureClifford Wolf2016-04-213-8/+8
* Cleanup abstract modules at end of "hierarchy -top"Clifford Wolf2016-03-211-2/+0
* Added "submod -copy"Clifford Wolf2016-01-081-13/+28
* Added "singleton" passClifford Wolf2015-11-072-0/+102
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-5/+5
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1
* Keep modules with $assume (like $assert)Clifford Wolf2015-07-251-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-022-5/+5
* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-041-2/+2
* documentation improvementsClifford Wolf2015-03-291-1/+1
* Added hierarchy -auto-topClifford Wolf2015-03-181-1/+33
* Fixed bug in "hierarchy" for parametric designsClifford Wolf2015-03-041-20/+19
* Cosmetic fixes in "hierarchy" for blackbox modulesClifford Wolf2015-02-151-2/+4
* Fixed pattern matching in "hierarchy -generate"Clifford Wolf2015-01-041-2/+2
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-2/+2
* Fixed off-by-one bug in "hierarchy -check" for positional module argsClifford Wolf2014-12-241-2/+2
* Checking existence of ports in "hierarchy -check"Clifford Wolf2014-12-191-0/+13
* Fixed bug in "hierarchy -top" with array of instancesClifford Wolf2014-11-271-3/+10
* Added log_warning() APIClifford Wolf2014-11-091-2/+2
* Various win32 / vs build fixesClifford Wolf2014-10-171-2/+2
* Header changes so it will compile on VSWilliam Speirs2014-10-171-1/+5
* Do not the 'z' modifier in format string (another win32 fix)Clifford Wolf2014-10-111-1/+1
* Moved patmatch() to yosys.ccClifford Wolf2014-10-101-1/+0
* Replaced fnmatch() with patmatch()Clifford Wolf2014-10-101-5/+4
* set "keep" on modules with $assert cells in "hierarchy"Clifford Wolf2014-09-301-0/+30
* namespace YosysClifford Wolf2014-09-272-11/+17
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-4/+4
* Added module->portsClifford Wolf2014-08-142-4/+5
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-021-1/+1
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-022-20/+20
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-1/+1
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-312-2/+2
* Allow "hierarchy -generate" for $__ cellsClifford Wolf2014-07-291-1/+3
* Using log_assert() instead of assert()Clifford Wolf2014-07-282-3/+3
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-272-36/+36
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-272-8/+8
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-272-5/+5
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-262-21/+23
* Manual fixes for new cell connections APIClifford Wolf2014-07-262-5/+5
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-262-11/+11
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-262-11/+11
* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-261-4/+1
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-8/+6
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-231-4/+4
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-221-1/+1
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-222-4/+4
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-222-4/+4
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