iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fitting help messages to 80 character width	KrystalDelusion	2022-08-24	1	-2/+2
*	Add the $anyinit cell and the formalff pass	Jannis Harder	2022-08-16	1	-0/+1
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
*	Use C++11 final/override keywords.	whitequark	2020-06-18	1	-2/+2
*	Use more descriptive variable name.	Alberto Gonzalez	2020-04-06	1	-2/+2
*	Clean up `passes/hierarchy/submod.cc`.	Alberto Gonzalez	2020-04-05	1	-25/+20
*	kernel: big fat patch to use more ID::, otherwise ID()	Eddie Hung	2020-04-02	1	-8/+8
*	Use pool instead of std::set for determinism	Eddie Hung	2019-12-02	1	-1/+1
*	Move \init signal for non-port signals as long as internally driven	Eddie Hung	2019-11-28	1	-1/+1
*	Fix multiple driver issue	Eddie Hung	2019-11-27	1	-2/+7
*	Do not replace constants with same wire	Eddie Hung	2019-11-27	1	-7/+3
*	Cleanup	Eddie Hung	2019-11-27	1	-5/+3
*	Check for nullptr	Eddie Hung	2019-11-27	1	-1/+1
*	Stray log_dump	Eddie Hung	2019-11-27	1	-1/+0
*	Revert "submod to bitty rather bussy, for bussy wires used as input and output"	Eddie Hung	2019-11-27	1	-40/+71
*	Promote output wires in sigmap so that can be detected	Eddie Hung	2019-11-26	1	-8/+4
*	Fix submod -hidden	Eddie Hung	2019-11-26	1	-5/+6
*	Add -hidden option to submod	Eddie Hung	2019-11-26	1	-11/+25
*	Update docs with bullet points	Eddie Hung	2019-11-26	1	-10/+9
*	Move \init from source wire to submod if output port	Eddie Hung	2019-11-25	1	-0/+7
*	submod to bitty rather bussy, for bussy wires used as input and output	Eddie Hung	2019-11-22	1	-48/+39
*	Constant driven signals are also an input to submodules	Eddie Hung	2019-11-22	1	-2/+10
*	Oops	Eddie Hung	2019-11-22	1	-1/+0
*	sigmap(wire) should inherit port_output status of POs	Eddie Hung	2019-11-22	1	-1/+19
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Minor bugfix in submod	Clifford Wolf	2016-11-09	1	-0/+1
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-3/+3
*	Added "submod -copy"	Clifford Wolf	2016-01-08	1	-13/+28
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Added log_warning() API	Clifford Wolf	2014-11-09	1	-2/+2
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
*	Added module->ports	Clifford Wolf	2014-08-14	1	-4/+3
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-5/+5
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-1/+1
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	1	-1/+1
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+1
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-6/+6
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-3/+3
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-17/+22
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-3/+3
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-6/+6
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-6/+6
*	Added copy-constructor-like module->addCell(name, other) method	Clifford Wolf	2014-07-26	1	-4/+1
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-8/+6
*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	1	-4/+4
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-2/+2
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-2/+2
*	Added call_on_selection() and call_on_module() API	Clifford Wolf	2014-07-20	1	-1/+1