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author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 14:32:50 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:58:23 +0200 |
commit | b7dda723022ad00c6c0089be888eab319953faa8 (patch) | |
tree | 4fe12ce120f1809891dc4cbd862bbcdab0e90fcc /passes/hierarchy/submod.cc | |
parent | cd6574ecf652901573cbc6b89e1a59dd383ec496 (diff) | |
download | yosys-b7dda723022ad00c6c0089be888eab319953faa8.tar.gz yosys-b7dda723022ad00c6c0089be888eab319953faa8.tar.bz2 yosys-b7dda723022ad00c6c0089be888eab319953faa8.zip |
Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
Diffstat (limited to 'passes/hierarchy/submod.cc')
-rw-r--r-- | passes/hierarchy/submod.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index df5fd8e37..d72ebb127 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -79,11 +79,11 @@ struct SubmodWorker wire_flags.clear(); for (RTLIL::Cell *cell : submod.cells) { if (ct.cell_known(cell->type)) { - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false); } else { log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) flag_signal(conn.second, true, true, true, false, false); } } @@ -92,11 +92,11 @@ struct SubmodWorker if (submod.cells.count(cell) > 0) continue; if (ct.cell_known(cell->type)) { - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) flag_signal(conn.second, false, false, false, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first)); } else { flag_found_something = false; - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) flag_signal(conn.second, false, false, false, true, true); if (flag_found_something) log("WARNING: Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str()); @@ -163,7 +163,7 @@ struct SubmodWorker for (RTLIL::Cell *cell : submod.cells) { RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell); - for (auto &conn : new_cell->connections_) + for (auto &conn : new_cell->connections()) for (auto &bit : conn.second) if (bit.wire != NULL) { assert(wire_flags.count(bit.wire) > 0); @@ -180,7 +180,7 @@ struct SubmodWorker RTLIL::Wire *old_wire = it.first; RTLIL::Wire *new_wire = it.second.new_wire; if (new_wire->port_id > 0) - new_cell->connections_[new_wire->name] = RTLIL::SigSpec(old_wire); + new_cell->connections()[new_wire->name] = RTLIL::SigSpec(old_wire); } } |