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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 16:07:47 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-25 16:07:47 -0800 |
| commit | 0d7ba77426b5ede6eae76059d8182ab096041ff2 (patch) | |
| tree | b342bb2dad10eaa2670e9d043e9545f165f0b4e6 /passes/hierarchy/submod.cc | |
| parent | dd317c92808a73e61e771a123fc4377d3fb78af2 (diff) | |
| download | yosys-0d7ba77426b5ede6eae76059d8182ab096041ff2.tar.gz yosys-0d7ba77426b5ede6eae76059d8182ab096041ff2.tar.bz2 yosys-0d7ba77426b5ede6eae76059d8182ab096041ff2.zip | |
Move \init from source wire to submod if output port
Diffstat (limited to 'passes/hierarchy/submod.cc')
| -rw-r--r-- | passes/hierarchy/submod.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 212932e46..7952c2dd6 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -162,6 +162,13 @@ struct SubmodWorker new_wire->port_input = new_wire_port_input; new_wire->port_output = new_wire_port_output; new_wire->attributes = wire->attributes; + if (new_wire->port_output) { + auto it = wire->attributes.find(ID(init)); + if (it != wire->attributes.end()) { + new_wire->attributes[ID(init)] = it->second[bit.offset]; + it->second[bit.offset] = State::Sx; + } + } if (new_wire->port_input && new_wire->port_output) log(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str()); |