| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Use C++11 final/override keywords. | whitequark | 2020-06-18 | 1 | -2/+2 |
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| * | Use more descriptive variable name. | Alberto Gonzalez | 2020-04-06 | 1 | -2/+2 |
| | | | | | Co-Authored-By: whitequark <whitequark@whitequark.org> | ||||
| * | Clean up `passes/hierarchy/submod.cc`. | Alberto Gonzalez | 2020-04-05 | 1 | -25/+20 |
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| * | kernel: big fat patch to use more ID::*, otherwise ID(*) | Eddie Hung | 2020-04-02 | 1 | -8/+8 |
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| * | Use pool instead of std::set for determinism | Eddie Hung | 2019-12-02 | 1 | -1/+1 |
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| * | Move \init signal for non-port signals as long as internally driven | Eddie Hung | 2019-11-28 | 1 | -1/+1 |
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| * | Fix multiple driver issue | Eddie Hung | 2019-11-27 | 1 | -2/+7 |
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| * | Do not replace constants with same wire | Eddie Hung | 2019-11-27 | 1 | -7/+3 |
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| * | Cleanup | Eddie Hung | 2019-11-27 | 1 | -5/+3 |
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| * | Check for nullptr | Eddie Hung | 2019-11-27 | 1 | -1/+1 |
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| * | Stray log_dump | Eddie Hung | 2019-11-27 | 1 | -1/+0 |
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| * | Revert "submod to bitty rather bussy, for bussy wires used as input and output" | Eddie Hung | 2019-11-27 | 1 | -40/+71 |
| | | | | | This reverts commit cba3073026711e7683c46ba091c56a5c5a041a45. | ||||
| * | Promote output wires in sigmap so that can be detected | Eddie Hung | 2019-11-26 | 1 | -8/+4 |
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| * | Fix submod -hidden | Eddie Hung | 2019-11-26 | 1 | -5/+6 |
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| * | Add -hidden option to submod | Eddie Hung | 2019-11-26 | 1 | -11/+25 |
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| * | Update docs with bullet points | Eddie Hung | 2019-11-26 | 1 | -10/+9 |
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| * | Move \init from source wire to submod if output port | Eddie Hung | 2019-11-25 | 1 | -0/+7 |
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| * | submod to bitty rather bussy, for bussy wires used as input and output | Eddie Hung | 2019-11-22 | 1 | -48/+39 |
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| * | Constant driven signals are also an input to submodules | Eddie Hung | 2019-11-22 | 1 | -2/+10 |
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| * | Oops | Eddie Hung | 2019-11-22 | 1 | -1/+0 |
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| * | sigmap(wire) should inherit port_output status of POs | Eddie Hung | 2019-11-22 | 1 | -1/+19 |
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| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | Minor bugfix in submod | Clifford Wolf | 2016-11-09 | 1 | -0/+1 |
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| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -3/+3 |
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| * | Added "submod -copy" | Clifford Wolf | 2016-01-08 | 1 | -13/+28 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
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| * | Added log_warning() API | Clifford Wolf | 2014-11-09 | 1 | -2/+2 |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
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| * | Added module->ports | Clifford Wolf | 2014-08-14 | 1 | -4/+3 |
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| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -5/+5 |
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| * | Renamed port access function on RTLIL::Cell, added param access functions | Clifford Wolf | 2014-07-31 | 1 | -1/+1 |
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| * | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 | 1 | -1/+1 |
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| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -1/+1 |
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| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -6/+6 |
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| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -3/+3 |
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| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -1/+1 |
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| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -17/+22 |
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| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -3/+3 |
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| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -6/+6 |
| | | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | ||||
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -6/+6 |
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| * | Added copy-constructor-like module->addCell(name, other) method | Clifford Wolf | 2014-07-26 | 1 | -4/+1 |
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| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -8/+6 |
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| * | Fixed all users of SigSpec::chunks_rw() and removed it | Clifford Wolf | 2014-07-23 | 1 | -4/+4 |
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| * | SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵ | Clifford Wolf | 2014-07-22 | 1 | -1/+1 |
| | | | | | created interim RTLIL::SigSpec::chunks_rw() | ||||
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 | 1 | -2/+2 |
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| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 | 1 | -2/+2 |
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| * | Added call_on_selection() and call_on_module() API | Clifford Wolf | 2014-07-20 | 1 | -1/+1 |
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| * | Moved some passes to other source directories | Clifford Wolf | 2014-02-08 | 1 | -0/+350 |
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