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* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
* Use more descriptive variable name.Alberto Gonzalez2020-04-061-2/+2
* Clean up `passes/hierarchy/submod.cc`.Alberto Gonzalez2020-04-051-25/+20
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-8/+8
* Use pool instead of std::set for determinismEddie Hung2019-12-021-1/+1
* Move \init signal for non-port signals as long as internally drivenEddie Hung2019-11-281-1/+1
* Fix multiple driver issueEddie Hung2019-11-271-2/+7
* Do not replace constants with same wireEddie Hung2019-11-271-7/+3
* CleanupEddie Hung2019-11-271-5/+3
* Check for nullptrEddie Hung2019-11-271-1/+1
* Stray log_dumpEddie Hung2019-11-271-1/+0
* Revert "submod to bitty rather bussy, for bussy wires used as input and output"Eddie Hung2019-11-271-40/+71
* Promote output wires in sigmap so that can be detectedEddie Hung2019-11-261-8/+4
* Fix submod -hiddenEddie Hung2019-11-261-5/+6
* Add -hidden option to submodEddie Hung2019-11-261-11/+25
* Update docs with bullet pointsEddie Hung2019-11-261-10/+9
* Move \init from source wire to submod if output portEddie Hung2019-11-251-0/+7
* submod to bitty rather bussy, for bussy wires used as input and outputEddie Hung2019-11-221-48/+39
* Constant driven signals are also an input to submodulesEddie Hung2019-11-221-2/+10
* OopsEddie Hung2019-11-221-1/+0
* sigmap(wire) should inherit port_output status of POsEddie Hung2019-11-221-1/+19
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Minor bugfix in submodClifford Wolf2016-11-091-0/+1
* Added "yosys -D" featureClifford Wolf2016-04-211-3/+3
* Added "submod -copy"Clifford Wolf2016-01-081-13/+28
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Added log_warning() APIClifford Wolf2014-11-091-2/+2
* namespace YosysClifford Wolf2014-09-271-0/+4
* Added module->portsClifford Wolf2014-08-141-4/+3
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-5/+5
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-1/+1
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-311-1/+1
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-1/+1
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-6/+6
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-3/+3
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-17/+22
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-3/+3
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-6/+6
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-6/+6
* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-261-4/+1
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-251-8/+6
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-231-4/+4
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-221-1/+1
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-2/+2
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-2/+2
* Added call_on_selection() and call_on_module() APIClifford Wolf2014-07-201-1/+1
* Moved some passes to other source directoriesClifford Wolf2014-02-081-0/+350