iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06	4	-6/+6
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-1/+1
*	Removed references to yosys-svgviewer from docs	Clifford Wolf	2014-09-02	1	-2/+2
*	Using "xdot" instead of "yosys-svgviewer" in show command	Clifford Wolf	2014-09-02	1	-4/+3
*	Moved "share" and "wreduce" to passes/opt/	Clifford Wolf	2014-09-01	2	-354/+0
*	Implemented "rename -enumerate -pattern"	Clifford Wolf	2014-08-26	1	-4/+13
*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23	2	-6/+6
*	Added "stat -width"	Clifford Wolf	2014-08-22	1	-4/+37
*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22	2	-2/+16
*	Added "plugin" command	Clifford Wolf	2014-08-22	2	-0/+118
*	Added module->uniquify()	Clifford Wolf	2014-08-16	1	-4/+1
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-2/+2
*	Fixed build with gcc-4.6	Clifford Wolf	2014-08-07	1	-6/+6
*	Various fixes and improvements in wreduce pass	Clifford Wolf	2014-08-05	1	-29/+47
*	Removed old "constmap" from wreduce code	Clifford Wolf	2014-08-05	1	-3/+2
*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05	1	-4/+40
*	Cleanups and improvements in wreduce pass	Clifford Wolf	2014-08-05	1	-47/+77
*	Added mux support to wreduce command	Clifford Wolf	2014-08-05	1	-36/+82
*	Added "show -signed"	Clifford Wolf	2014-08-04	1	-5/+17
*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04	1	-4/+3
*	Progress in "wreduce" pass	Clifford Wolf	2014-08-03	1	-43/+16
*	Added "wreduce" command (work in progress)	Clifford Wolf	2014-08-03	2	-0/+253
*	Fixes in show command (related to new IdString)	Clifford Wolf	2014-08-03	1	-20/+18
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	3	-4/+4
*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	1	-3/+3
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	4	-19/+21
*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	3	-6/+6
*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	1	-3/+3
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	3	-10/+10
*	Added "trace" command	Clifford Wolf	2014-07-31	3	-2/+100
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	2	-4/+6
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-0/+4
*	Added write_file command	Clifford Wolf	2014-07-30	2	-0/+77
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	3	-5/+5
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	16	-62/+62
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	14	-38/+38
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	11	-35/+35
*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	2	-15/+9
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	4	-58/+25
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-1/+1
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	6	-10/+10
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	10	-33/+33
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	10	-33/+33
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	2	-13/+6
*	Various RTLIL::SigSpec related code cleanups	Clifford Wolf	2014-07-25	1	-3/+3
*	Disabled cover() for non-linux builds	Clifford Wolf	2014-07-25	1	-2/+5
*	Improvements in "cover" command	Clifford Wolf	2014-07-25	1	-11/+37
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-2/+2
*	Added "cover" command	Clifford Wolf	2014-07-24	3	-1/+117
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	4	-7/+1