Refactoring: Renamed RTLIL::Module::cells to cells_

14 files changed, 38 insertions, 38 deletions

diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index e97bf8fc1..49aa7c98d 100644
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -62,7 +62,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
 	if (!flag_global)
 		return;
 
-	for (auto &it : module->cells)
+	for (auto &it : module->cells_)
 	{
 		if (design->modules.count(it.second->type) == 0)
 			continue;
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc
index 99a28d4a0..6494ea6f6 100644
--- a/passes/cmds/connect.cc
+++ b/passes/cmds/connect.cc
@@ -29,7 +29,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
 
 	RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
 
-	for (auto &it : module->cells)
+	for (auto &it : module->cells_)
 	for (auto &port : it.second->connections_)
 		if (ct.cell_output(it.second->type, port.first))
 			sigmap(port.second).replace(sig, dummy_wire, &port.second);
@@ -169,14 +169,14 @@ struct ConnectPass : public Pass {
 			if (flag_nounset)
 				log_cmd_error("Cant use -port together with -nounset.\n");
 
-			if (module->cells.count(RTLIL::escape_id(port_cell)) == 0)
+			if (module->cells_.count(RTLIL::escape_id(port_cell)) == 0)
 				log_cmd_error("Can't find cell %s.\n", port_cell.c_str());
 
 			RTLIL::SigSpec sig;
 			if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr))
 				log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str());
 
-			module->cells.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig));
+			module->cells_.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig));
 		}
 		else
 			log_cmd_error("Expected -set, -unset, or -port.\n");
diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc
index 9faeffafa..cc8147c53 100644
--- a/passes/cmds/connwrappers.cc
+++ b/passes/cmds/connwrappers.cc
@@ -67,7 +67,7 @@ struct ConnwrappersWorker
 		std::map<RTLIL::SigBit, std::pair<bool, RTLIL::SigSpec>> extend_map;
 		SigMap sigmap(module);
 
-		for (auto &it : module->cells)
+		for (auto &it : module->cells_)
 		{
 			RTLIL::Cell *cell = it.second;
 
@@ -102,7 +102,7 @@ struct ConnwrappersWorker
 			}
 		}
 
-		for (auto &it : module->cells)
+		for (auto &it : module->cells_)
 		{
 			RTLIL::Cell *cell = it.second;
 
diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index 460dd9663..2c2c370dd 100644
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -103,7 +103,7 @@ struct DeletePass : public Pass {
 				if (design->selected(module, it.second))
 					delete_mems.insert(it.first);
 
-			for (auto &it : module->cells) {
+			for (auto &it : module->cells_) {
 				if (design->selected(module, it.second))
 					delete_cells.insert(it.second);
 				if ((it.second->type == "$memrd" || it.second->type == "$memwr") &&
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index e163e7243..c8b8160f1 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -36,7 +36,7 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
 			return;
 		}
 
-	for (auto &it : module->cells)
+	for (auto &it : module->cells_)
 		if (it.first == from_name) {
 			log("Renaming cell %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
 			module->rename(it.second, to_name);
@@ -114,13 +114,13 @@ struct RenamePass : public Pass {
 				module->wires_.swap(new_wires);
 
 				std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
-				for (auto &it : module->cells) {
+				for (auto &it : module->cells_) {
 					if (it.first[0] == '$' && design->selected(module, it.second))
 						do it.second->name = stringf("\\_%d_", counter++);
 						while (module->count_id(it.second->name) > 0);
 					new_cells[it.second->name] = it.second;
 				}
-				module->cells.swap(new_cells);
+				module->cells_.swap(new_cells);
 			}
 		}
 		else
@@ -144,13 +144,13 @@ struct RenamePass : public Pass {
 				module->wires_.swap(new_wires);
 
 				std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
-				for (auto &it : module->cells) {
+				for (auto &it : module->cells_) {
 					if (design->selected(module, it.second))
 						if (it.first[0] == '\\')
 							it.second->name = NEW_ID;
 					new_cells[it.second->name] = it.second;
 				}
-				module->cells.swap(new_cells);
+				module->cells_.swap(new_cells);
 			}
 		}
 		else
diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index 0b95fe024..a1c12f1ee 100644
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -48,7 +48,7 @@ struct ScatterPass : public Pass {
 			if (!design->selected(mod_it.second))
 				continue;
 
-			for (auto &c : mod_it.second->cells)
+			for (auto &c : mod_it.second->cells_)
 			for (auto &p : c.second->connections_)
 			{
 				RTLIL::Wire *wire = mod_it.second->addWire(NEW_ID, p.second.size());
diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc
index 7e2b2fc9f..c95043417 100644
--- a/passes/cmds/scc.cc
+++ b/passes/cmds/scc.cc
@@ -118,7 +118,7 @@ struct SccWorker
 			if (design->selected(module, it.second))
 				selectedSignals.add(sigmap(RTLIL::SigSpec(it.second)));
 
-		for (auto &it : module->cells)
+		for (auto &it : module->cells_)
 		{
 			RTLIL::Cell *cell = it.second;
 
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 0cabdc06b..306b7a5b1 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -167,7 +167,7 @@ static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs)
 		for (auto &it : mod->memories)
 			if (!lhs.selected_member(mod_it.first, it.first))
 				new_sel.selected_members[mod->name].insert(it.first);
-		for (auto &it : mod->cells)
+		for (auto &it : mod->cells_)
 			if (!lhs.selected_member(mod_it.first, it.first))
 				new_sel.selected_members[mod->name].insert(it.first);
 		for (auto &it : mod->processes)
@@ -185,7 +185,7 @@ static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs)
 	{
 		if (lhs.selected_whole_module(mod_it.first))
 		{
-			for (auto &cell_it : mod_it.second->cells)
+			for (auto &cell_it : mod_it.second->cells_)
 			{
 				if (design->modules.count(cell_it.second->type) == 0)
 					continue;
@@ -282,7 +282,7 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R
 				lhs.selected_members[mod->name].insert(it.first);
 			for (auto &it : mod->memories)
 				lhs.selected_members[mod->name].insert(it.first);
-			for (auto &it : mod->cells)
+			for (auto &it : mod->cells_)
 				lhs.selected_members[mod->name].insert(it.first);
 			for (auto &it : mod->processes)
 				lhs.selected_members[mod->name].insert(it.first);
@@ -395,7 +395,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
 			}
 		}
 
-		for (auto &cell : mod->cells)
+		for (auto &cell : mod->cells_)
 		for (auto &conn : cell.second->connections())
 		{
 			char last_mode = '-';
@@ -742,12 +742,12 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
 					sel.selected_members[mod->name].insert(it.first);
 		} else
 		if (arg_memb.substr(0, 2) == "c:") {
-			for (auto &it : mod->cells)
+			for (auto &it : mod->cells_)
 				if (match_ids(it.first, arg_memb.substr(2)))
 					sel.selected_members[mod->name].insert(it.first);
 		} else
 		if (arg_memb.substr(0, 2) == "t:") {
-			for (auto &it : mod->cells)
+			for (auto &it : mod->cells_)
 				if (match_ids(it.second->type, arg_memb.substr(2)))
 					sel.selected_members[mod->name].insert(it.first);
 		} else
@@ -763,7 +763,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
 			for (auto &it : mod->memories)
 				if (match_attr(it.second->attributes, arg_memb.substr(2)))
 					sel.selected_members[mod->name].insert(it.first);
-			for (auto &it : mod->cells)
+			for (auto &it : mod->cells_)
 				if (match_attr(it.second->attributes, arg_memb.substr(2)))
 					sel.selected_members[mod->name].insert(it.first);
 			for (auto &it : mod->processes)
@@ -771,7 +771,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
 					sel.selected_members[mod->name].insert(it.first);
 		} else
 		if (arg_memb.substr(0, 2) == "r:") {
-			for (auto &it : mod->cells)
+			for (auto &it : mod->cells_)
 				if (match_attr(it.second->parameters, arg_memb.substr(2)))
 					sel.selected_members[mod->name].insert(it.first);
 		} else {
@@ -783,7 +783,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
 			for (auto &it : mod->memories)
 				if (match_ids(it.first, arg_memb))
 					sel.selected_members[mod->name].insert(it.first);
-			for (auto &it : mod->cells)
+			for (auto &it : mod->cells_)
 				if (match_ids(it.first, arg_memb))
 					sel.selected_members[mod->name].insert(it.first);
 			for (auto &it : mod->processes)
@@ -1158,7 +1158,7 @@ struct SelectPass : public Pass {
 					for (auto &it : mod_it.second->memories)
 						if (sel->selected_member(mod_it.first, it.first))
 							LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first));
-					for (auto &it : mod_it.second->cells)
+					for (auto &it : mod_it.second->cells_)
 						if (sel->selected_member(mod_it.first, it.first))
 							LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first));
 					for (auto &it : mod_it.second->processes)
@@ -1225,7 +1225,7 @@ struct SelectPass : public Pass {
 					for (auto &it : mod_it.second->memories)
 						if (sel->selected_member(mod_it.first, it.first))
 							total_count++;
-					for (auto &it : mod_it.second->cells)
+					for (auto &it : mod_it.second->cells_)
 						if (sel->selected_member(mod_it.first, it.first))
 							total_count++;
 					for (auto &it : mod_it.second->processes)
@@ -1303,8 +1303,8 @@ struct CdPass : public Pass {
 			RTLIL::Module *module = NULL;
 			if (design->modules.count(design->selected_active_module) > 0)
 				module = design->modules.at(design->selected_active_module);
-			if (module != NULL && module->cells.count(modname) > 0)
-				modname = module->cells.at(modname)->type;
+			if (module != NULL && module->cells_.count(modname) > 0)
+				modname = module->cells_.at(modname)->type;
 		}
 
 		if (design->modules.count(modname) > 0) {
@@ -1376,7 +1376,7 @@ struct LsPass : public Pass {
 			RTLIL::Module *module = design->modules.at(design->selected_active_module);
 			counter += log_matches("wires", pattern, module->wires_);
 			counter += log_matches("memories", pattern, module->memories);
-			counter += log_matches("cells", pattern, module->cells);
+			counter += log_matches("cells", pattern, module->cells_);
 			counter += log_matches("processes", pattern, module->processes);
 		}
 
diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc
index 0b4f2a8a2..ea5221f6d 100644
--- a/passes/cmds/setattr.cc
+++ b/passes/cmds/setattr.cc
@@ -119,7 +119,7 @@ struct SetattrPass : public Pass {
 				if (design->selected(module, it.second))
 					do_setunset(it.second->attributes, setunset_list);
 
-			for (auto &it : module->cells)
+			for (auto &it : module->cells_)
 				if (design->selected(module, it.second))
 					do_setunset(it.second->attributes, setunset_list);
 
@@ -171,7 +171,7 @@ struct SetparamPass : public Pass {
 			if (!design->selected(module))
 				continue;
 
-			for (auto &it : module->cells)
+			for (auto &it : module->cells_)
 				if (design->selected(module, it.second))
 					do_setunset(it.second->parameters, setunset_list);
 		}
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 82dc1d999..e7779415d 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -134,7 +134,7 @@ struct SetundefPass : public Pass {
 						undriven_signals.add(sigmap(it.second));
 
 				CellTypes ct(design);
-				for (auto &it : module->cells)
+				for (auto &it : module->cells_)
 				for (auto &conn : it.second->connections())
 					if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
 						undriven_signals.del(sigmap(conn.second));
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 1feb90afb..18af8dfce 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -337,7 +337,7 @@ struct ShowWorker
 			fprintf(f, "}\n");
 		}
 
-		for (auto &it : module->cells)
+		for (auto &it : module->cells_)
 		{
 			if (!design->selected_member(module->name, it.first))
 				continue;
@@ -516,7 +516,7 @@ struct ShowWorker
 					log("Skipping blackbox module %s.\n", id2cstr(module->name));
 					continue;
 				} else
-				if (module->cells.empty() && module->connections().empty() && module->processes.empty()) {
+				if (module->cells_.empty() && module->connections().empty() && module->processes.empty()) {
 					log("Skipping empty module %s.\n", id2cstr(module->name));
 					continue;
 				} else
@@ -695,7 +695,7 @@ struct ShowPass : public Pass {
 			for (auto &mod_it : design->modules) {
 				if (mod_it.second->get_bool_attribute("\\blackbox"))
 					continue;
-				if (mod_it.second->cells.empty() && mod_it.second->connections().empty())
+				if (mod_it.second->cells_.empty() && mod_it.second->connections().empty())
 					continue;
 				if (design->selected_module(mod_it.first))
 					modcount++;
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index 691d972cf..dcd2f819f 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -158,7 +158,7 @@ struct SpliceWorker
 				driven_bits.push_back(RTLIL::State::Sm);
 			}
 
-		for (auto &it : module->cells)
+		for (auto &it : module->cells_)
 		for (auto &conn : it.second->connections())
 			if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) {
 				RTLIL::SigSpec sig = sigmap(conn.second);
@@ -179,7 +179,7 @@ struct SpliceWorker
 				if (design->selected(module, it.second))
 					selected_bits.add(sigmap(it.second));
 
-		for (auto &it : module->cells) {
+		for (auto &it : module->cells_) {
 			if (!sel_by_wire && !design->selected(module, it.second))
 				continue;
 			for (auto &conn : it.second->connections_)
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index accb178ba..0998a1622 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -131,7 +131,7 @@ struct SplitnetsPass : public Pass {
 
 				std::map<RTLIL::Wire*, std::set<int>> split_wires_at;
 
-				for (auto &c : module->cells)
+				for (auto &c : module->cells_)
 				for (auto &p : c.second->connections())
 				{
 					if (!ct.cell_known(c.second->type))
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index fabf1a73f..153226ab5 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -90,7 +90,7 @@ namespace
 				num_memory_bits += it.second->width * it.second->size;
 			}
 
-			for (auto &it : mod->cells) {
+			for (auto &it : mod->cells_) {
 				if (!design->selected(mod, it.second))
 					continue;
 				num_cells++;