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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-16 23:50:36 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-16 23:50:36 +0200 |
| commit | 7f734ecc098a2a113ced835cefc9d4e1982f08d0 (patch) | |
| tree | 0e73ad74bd4602da7a6a1a3b264e1842deccac18 /passes/cmds | |
| parent | f82c978e08604c596b034fb6e74ac34c78b9364b (diff) | |
| download | yosys-7f734ecc098a2a113ced835cefc9d4e1982f08d0.tar.gz yosys-7f734ecc098a2a113ced835cefc9d4e1982f08d0.tar.bz2 yosys-7f734ecc098a2a113ced835cefc9d4e1982f08d0.zip | |
Added module->uniquify()
Diffstat (limited to 'passes/cmds')
| -rw-r--r-- | passes/cmds/splitnets.cc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index a3daf2398..cef0a272e 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -46,10 +46,7 @@ struct SplitnetsWorker if (format.size() > 1) new_wire_name += format.substr(1, 1); - while (module->count_id(new_wire_name) > 0) - new_wire_name += "_"; - - RTLIL::Wire *new_wire = module->addWire(new_wire_name, width); + RTLIL::Wire *new_wire = module->addWire(module->uniquify(new_wire_name), width); new_wire->port_id = wire->port_id; new_wire->port_input = wire->port_input; new_wire->port_output = wire->port_output; |