iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	1	-3/+3
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Re-created command-reference-manual.tex, copied some doc fixes to online help	Clifford Wolf	2015-08-14	1	-1/+1
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	1	-1/+1
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-1/+1
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-3/+3
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-3/+3
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-5/+5
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-5/+5
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-1/+1
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-1/+1
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	1	-1/+1
*	Added generic RTLIL::SigSpec::parse_sel() with support for selection variables	Clifford Wolf	2014-02-06	1	-3/+3
*	Added "connect" command	Clifford Wolf	2014-01-03	1	-0/+185