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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 01:51:45 +0200 |
| commit | 4c4b6021562c598c4510831bd547edaa97d14dac (patch) | |
| tree | 7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /passes/cmds/connect.cc | |
| parent | f9946232adf887e5aa4a48c64f88eaa17e424009 (diff) | |
| download | yosys-4c4b6021562c598c4510831bd547edaa97d14dac.tar.gz yosys-4c4b6021562c598c4510831bd547edaa97d14dac.tar.bz2 yosys-4c4b6021562c598c4510831bd547edaa97d14dac.zip | |
Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'passes/cmds/connect.cc')
| -rw-r--r-- | passes/cmds/connect.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 99a28d4a0..6494ea6f6 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -29,7 +29,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size()); - for (auto &it : module->cells) + for (auto &it : module->cells_) for (auto &port : it.second->connections_) if (ct.cell_output(it.second->type, port.first)) sigmap(port.second).replace(sig, dummy_wire, &port.second); @@ -169,14 +169,14 @@ struct ConnectPass : public Pass { if (flag_nounset) log_cmd_error("Cant use -port together with -nounset.\n"); - if (module->cells.count(RTLIL::escape_id(port_cell)) == 0) + if (module->cells_.count(RTLIL::escape_id(port_cell)) == 0) log_cmd_error("Can't find cell %s.\n", port_cell.c_str()); RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr)) log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str()); - module->cells.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig)); + module->cells_.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig)); } else log_cmd_error("Expected -set, -unset, or -port.\n"); |