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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:15:14 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:37 +0200 |
| commit | 4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 (patch) | |
| tree | 27801c4b0171a2491ff6817ebb6d2a1d1484c086 /passes/cmds/connect.cc | |
| parent | 16e5ae0b92ac4b7568cb11a769e612e152c0042e (diff) | |
| download | yosys-4b4048bc5feba1ab05c7a63f12c0a17879cb7e04.tar.gz yosys-4b4048bc5feba1ab05c7a63f12c0a17879cb7e04.tar.bz2 yosys-4b4048bc5feba1ab05c7a63f12c0a17879cb7e04.zip | |
SigSpec refactoring: using the accessor functions everywhere
Diffstat (limited to 'passes/cmds/connect.cc')
| -rw-r--r-- | passes/cmds/connect.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index f8f9e0590..dcd5fc96b 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -27,7 +27,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & { CellTypes ct(design); - RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.__width); + RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size()); for (auto &it : module->cells) for (auto &port : it.second->connections) |