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author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:57:57 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 15:58:23 +0200 |
commit | f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (patch) | |
tree | e4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /passes/cmds/connect.cc | |
parent | b7dda723022ad00c6c0089be888eab319953faa8 (diff) | |
download | yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.tar.gz yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.tar.bz2 yosys-f8fdc47d3361c1a3445a9357ca26cfe75907d6b0.zip |
Manual fixes for new cell connections API
Diffstat (limited to 'passes/cmds/connect.cc')
-rw-r--r-- | passes/cmds/connect.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index ffe7a5efa..99a28d4a0 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -30,11 +30,11 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size()); for (auto &it : module->cells) - for (auto &port : it.second->connections()) + for (auto &port : it.second->connections_) if (ct.cell_output(it.second->type, port.first)) sigmap(port.second).replace(sig, dummy_wire, &port.second); - for (auto &conn : module->connections()) + for (auto &conn : module->connections_) sigmap(conn.first).replace(sig, dummy_wire, &conn.first); } @@ -176,7 +176,7 @@ struct ConnectPass : public Pass { if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr)) log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str()); - module->cells.at(RTLIL::escape_id(port_cell))->connections()[RTLIL::escape_id(port_port)] = sigmap(sig); + module->cells.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig)); } else log_cmd_error("Expected -set, -unset, or -port.\n"); |