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* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-3/+3
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-141-1/+1
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* namespace YosysClifford Wolf2014-09-271-0/+4
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-1/+1
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-3/+3
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-3/+3
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-5/+5
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-5/+5
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-1/+1
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-1/+1
* Removed deprecated module->new_wire()Clifford Wolf2014-07-211-1/+1
* Added generic RTLIL::SigSpec::parse_sel() with support for selection variablesClifford Wolf2014-02-061-3/+3
* Added "connect" commandClifford Wolf2014-01-031-0/+185