iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵	Clifford Wolf	2014-08-16	1	-25/+161
\| \| \| \|	$_OAI4_
*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15	1	-2/+2
\|
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-2/+2
\|
*	Added module->ports	Clifford Wolf	2014-08-14	1	-2/+1
\|
*	Added "abc -D" for setting delay target	Clifford Wolf	2014-08-14	1	-5/+18
\|
*	Filter ANSI escape sequences from ABC output	Clifford Wolf	2014-08-13	1	-0/+15
\|
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-1/+1
\|
*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	1	-1/+1
\|
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	2	-37/+37
\|
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	1	-1/+1
\|
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-2/+2
\|
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-5/+4
\|
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	2	-3/+3
\|
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-6/+6
\|
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	2	-34/+34
\|
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	2	-22/+8
\|
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	2	-2/+2
\|
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	2	-48/+48
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	2	-48/+48
\|
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	2	-50/+16
\|
*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-19/+19
\|
*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-3/+0
\|
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-30/+23
\|
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-1/+1
\|
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-1/+1
\|
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3	Clifford Wolf	2014-07-23	1	-1/+1
\|
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	2	-39/+39
\|
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	2	-39/+39
\|
*	- kernel/register.h, kernel/driver.cc: refactor ↵	Siesh1oo	2014-03-12	1	-1/+1
\| \| \| \| \| \| \|	rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems. - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
*	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11	1	-2/+7
\| \| \| \|	(see https://github.com/cliffordwolf/yosys/pull/28)
*	Fixed memory corruption in passes/abc/blifparse.cc	Clifford Wolf	2014-03-11	1	-1/+1
\|
*	Verbose reading of liberty and constr files in ABC pass	Clifford Wolf	2014-03-09	1	-2/+2
\|
*	Added abc -keepff option	Clifford Wolf	2014-02-14	1	-5/+18
\|
*	updated default ABC command strings	Clifford Wolf	2014-02-13	1	-4/+4
\|
*	Updated ABC	Clifford Wolf	2014-02-13	1	-0/+23
\|
*	Removed double blanks in ABC default command sequences	Clifford Wolf	2014-02-13	1	-4/+4
\|
*	Updated ABC and some related changes	Clifford Wolf	2014-02-13	1	-10/+31
\|
*	Updated ABC to rev e97a6e1d59b9	Clifford Wolf	2014-02-12	1	-4/+49
\|
*	Added support for "keep" attribute to abc pass	Clifford Wolf	2014-02-08	1	-1/+1
\|
*	Re-enabled abc "retime" after sorting yout the yosys-bigsim problem	Clifford Wolf	2014-02-07	1	-7/+0
\|
*	Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim ↵	Clifford Wolf	2014-02-06	1	-0/+7
\| \| \| \|	failed)
*	Added "retime" to standard ABC recipes	Clifford Wolf	2014-02-06	1	-4/+4
\|
*	Added support for inline commands to abc -script	Clifford Wolf	2014-02-04	1	-39/+75
\|
*	Fixed use of limited length buffer in ABC blif parser	Clifford Wolf	2013-12-31	1	-7/+16
\|
*	Added abc -dff and -clk support	Clifford Wolf	2013-12-31	3	-34/+173
\|
*	Now using BLIF as ABC input format	Clifford Wolf	2013-12-31	1	-37/+54
\|
*	Always use BLIF as ABC output format	Clifford Wolf	2013-12-31	5	-268/+31
\|
*	Tighter integration of ABC build	Clifford Wolf	2013-11-27	1	-0/+2
\|
*	Updated abc	Clifford Wolf	2013-11-21	1	-10/+27
\|
*	Renamed temp module generated by "abc" pass from "logic" to "netlist"	Clifford Wolf	2013-11-19	2	-6/+6
\|