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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 14:11:39 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 14:11:39 +0200 |
| commit | e6d33513a5b809facc6e3e5e75d2248bfa94f82b (patch) | |
| tree | bcee5a22fc9ac7dca5b871ce667114e5f15d07d0 /passes/abc | |
| parent | 1cb25c05b37b0172dbc50e140fe20f25d973dd8a (diff) | |
| download | yosys-e6d33513a5b809facc6e3e5e75d2248bfa94f82b.tar.gz yosys-e6d33513a5b809facc6e3e5e75d2248bfa94f82b.tar.bz2 yosys-e6d33513a5b809facc6e3e5e75d2248bfa94f82b.zip | |
Added module->design and cell->module, wire->module pointers
Diffstat (limited to 'passes/abc')
| -rw-r--r-- | passes/abc/blifparse.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 4bcbc0131..e10cb109f 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -60,7 +60,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) int port_count = 0; module->name = "\\netlist"; - design->modules_[module->name] = module; + design->add(module); size_t buffer_size = 4096; char *buffer = (char*)malloc(buffer_size); |