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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 09:00:16 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 09:34:47 +0200 |
| commit | 260c19ec5a3adb292158658dd69a352b9325ab64 (patch) | |
| tree | a5ee152f61ce7952afc7cc7ffaaef66b98511c3a /passes/abc | |
| parent | c61467a32c4bd3ec4b9e0cb6d36d602f0e4dea81 (diff) | |
| download | yosys-260c19ec5a3adb292158658dd69a352b9325ab64.tar.gz yosys-260c19ec5a3adb292158658dd69a352b9325ab64.tar.bz2 yosys-260c19ec5a3adb292158658dd69a352b9325ab64.zip | |
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
Diffstat (limited to 'passes/abc')
| -rw-r--r-- | passes/abc/abc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 2d921b7be..e7371ec52 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -466,7 +466,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std clk_str = clk_str.substr(1); } if (module->wires.count(RTLIL::escape_id(clk_str)) != 0) - clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1)); + clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 1, 0)); } if (dff_mode && clk_sig.size() == 0) |