diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-08-14 16:13:42 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-14 16:22:52 +0200 |
| commit | 1bf7a18fec76cf46a5b8710a75371e23b68d147d (patch) | |
| tree | ea445edda6c4bc0fa670effce4ef1b0eaf906258 /passes/abc | |
| parent | 746aac540b815099c6a63077010555369d7fdd5a (diff) | |
| download | yosys-1bf7a18fec76cf46a5b8710a75371e23b68d147d.tar.gz yosys-1bf7a18fec76cf46a5b8710a75371e23b68d147d.tar.bz2 yosys-1bf7a18fec76cf46a5b8710a75371e23b68d147d.zip | |
Added module->ports
Diffstat (limited to 'passes/abc')
| -rw-r--r-- | passes/abc/blifparse.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 1891a7450..bc8f343a5 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -58,7 +58,6 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) RTLIL::Const *lutptr = NULL; RTLIL::State lut_default_state = RTLIL::State::Sx; - int port_count = 0; module->name = "\\netlist"; design->add(module); @@ -91,6 +90,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) continue; if (!strcmp(cmd, ".end")) { + module->fixup_ports(); free(buffer); return design; } @@ -99,7 +99,6 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) char *p; while ((p = strtok(NULL, " \t\r\n")) != NULL) { RTLIL::Wire *wire = module->addWire(stringf("\\%s", p)); - wire->port_id = ++port_count; if (!strcmp(cmd, ".inputs")) wire->port_input = true; else |